Uttam Shyamalindu Ghoshal

A 1.0-GHz single-issue 64-bit powerPC integer processor

This 64 b single-issue integer processor, comprised of about one million transistors, is fabricated in a 0.15 /spl mu/m effective channel length, six-metal-layer CMOS technology. Intended as a vehicle to explore circuit, clocking, microarchitecture, and methodology options for high-frequency processors, the processor prototype implements 60 fixed-point compare, logical, arithmetic, and rotate-merge-mask instructions of the PowerPC instruction-set architecture with single-cycle latency. The processor executes programs written in this instruction subset from cache with a 1 ns cycle. In addition, the prototype implements 36 PowerPC load/store instructions that execute as single-cycle operations (zero wait cycles) with 1.15 ns latency. Full data forwarding and full at speed scan testing are supported.

Study of interface effects in thermoelectric microrefrigerators

Interface phenomena play a vital role in thermoelectric (TE) microrefrigerators. The present study employs a phenomenological model to examine the behavior of TE refrigerators as a function of thermal and electrical contact resistance, boundary Seebeck coefficient, and heat sink conductance. We modify the conventional definition of the figure of merit to capture the interface effects. A finite temperature drop across the interface between a metal electrode and a thermoelement is found to strongly influence the boundary Seebeck effect. Interface engineering can potentially improve the overall performance of TE microrefrigerators.

Design methodology for a 1.0 GHz microprocessor

This paper describes the design methodology used to build an experimental 1.0 GigaHertz PowerPC integer microprocessor at IBMs Austin Research Laboratory. The high frequency requirements dictated the chip composition to be almost entirely custom macros using dynamic circuit techniques. The methodology presented will cover design and verification tools as well as circuit constraints and microarchitecture philosophy. The microarchitecture, circuits and tools were defined by the high frequency requirements of the processor as well as the aggressive design schedule and size of the design team.

Enhanced thermoelectric cooling at cold junction interfaces

We describe a thermoelectric device structure that confines the thermal gradients and electric fields at the boundaries of the cold end, and exploits the reduction of thermal conductivity at the interfaces and the poor electron-phonon coupling at the junctions. The measured temperature–current and voltage–current characteristics of a prototype cold point-contact thermoelectric cooler based on a p-type Bi0.5Sb1.5Te3 and n-type Bi2Te2.9Se0.1 material system indicate an enhanced thermoelectric figure-of-merit ZT in the range of 1.4–1.7 at room temperature.

Refrigeration technologies for sub-ambient temperature operation of computing systems

Thermal management issues are central to development of computing systems in the next millennium. In light of performance and reliability limitations facing scaling of CMOS devices below 100 nm channel lengths at typical operating temperatures (60-100/spl deg/C), many system designers are seriously considering low temperature operation of high performance processors. Two different refrigeration technologies being developed for server applications are described here.

Physical design challenges for performance

Recent trends in high performance microprocessor design suggest that complex gigahertz processors based on deep-submicron CMOS technologies will be practical in the near future. It is also certain that integration complexity will result in ever-increasing demand for interconnection connectivity and bandwidths. Front-end chip planning, back-end interconnect design, and global electrical analysis issues will be at the forefront.

Inductance analysis of on-chip interconnects [deep submicron CMOS]

It is generally believed that inductance analysis of on-chip interconnect becomes important when the clock frequency of circuits rises above GHz level. In this paper we show that this perception is not true. It becomes necessary to consider the inductive effects in all circuits implemented in deep submicron CMOS technologies. For 0.25 /spl mu/m (lithography) technologies, where the supply voltage is expected to be in the range of 1.2-1.8 V, inductive effects are an important consideration regardless of system frequency. Furthermore, contrary to the popular belief we show that inductive effects are important even for highly resistive lines.

Advanced electronic microcoolers

We discuss the design issues in the development of thermoelectric microcoolers for sub-200 K spot cooling applications. We start with the scaling theory for conventional microcooler configurations, and describe the practical constraints placed by contact resistances, heat rejection methods, and entropy gradients at the interfaces. We also introduce the concepts of switched thermoelectric coolers that exploit the temporal differences in the slow evolution of Joule heat and instantaneous Peltier cooling, to attain large temperature differentials.

Design and characterization of cold point thermoelectric coolers

We describe structured point-contact thermoelectric devices that confine the thermal gradients and electric fields at the boundaries of the cold end, and exploits the reduction of thermal conductivity at the interfaces, tunneling properties of point contacts, and the poor electron-phonon coupling at the junctions. We propose a theory of the structured cold point metal-semiconductor contacts and detail the design of cold point thermoelectric coolers. Temperature and electrical measurements of prototype cold point coolers using bismuth chalcogenides in vacuum indicate doubling of the thermoelectric figure-of-merit ZT values to the range of 1.4-1.7 at room temperature.

Thermoelectric Mapping of Nanostructures

There is intense interest to develop nanowires [1] and superlattices [2] that may offer superior thermoelectric figure of merit for efficient energy conversion. Meanwhile, the advance of semiconductor processing techniques has yielded impurity-doped semiconductor nanostructures with a doped region as small as a few nanometers. These include shallow junction Si field-effect transistors, strained Si/SiGe/Ge heterostructures and quantum dots, III-V heterostructures, and doped nanowires and nanotubes. Due to various size confinement effects, these doped semiconductor nanostructures often have unique electrical, optoelectronic, or thermoelectric properties that may lead to a wide range of applications. In contrast to the progress made in synthesizing thermoelectric nanostructures and in fabricating doped semiconductor nanostructures, the ability to quantify thermoelectric property and carrier concentration in comparable length scale has been lagging behind. For example, the 1997 U.S. Roadmap of Semiconductors from the Semiconductor Industry Association (SIA) defines the need for nanometer-scale measurements of carrier concentration profiles [3]. Though progress has been made, currently no technique can satisfy the requirements posted by the SIA roadmap due to the lack of either spatial resolution or accuracy.Copyright