Chandra Tan

Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems

Adaptive computing systems (ACSs) can serve as flexible hardware accelerators for applications in domains such as image and digital signal processing. However, the mapping of applications onto ACSs using the traditional methods can take months for a hardware engineer to develop and debug. To enable application designers to map their applications automatically onto ACSs, a software design environment called CHAMPION was developed at the University of Tennessee. This environment permits high-level design entry using the Cantata graphical programming environment from KRI and hides from the user the low-level details of the hardware architecture. Thus, ACSs can be utilized by a wider audience and application development can be accomplished in less time. Furthermore, CHAMPION provides the means to map onto multiple ACS platforms, thereby exploiting rapid advances being made in hardware.

Design implementation of intrinsic area array ICs

Arranging I/O in a matrix array over the core circuitry of an IC generally provides 5-10 times more I/O than the traditional method of restricting pads to the periphery. This approach also minimizes overall die size. This method was pioneered by IBM over thirty years ago and has recently become attractive for new designs requiring several hundred I/O. In this paper we describe the development of a new area-array pad router which differs from other approaches in that no additional metal layer is added (unless needed) and no redistribution is required. We describe the design guideline definition, data preparation, pad placement, pad assignment, pad routing, and output padframe generation of this technique. The results of applying this router are shown for sample designs requiring 112, 298 and 485 I/Os.

An intrinsic area-array pad router for ICs

Arranging I/Os in a matrix array over the core circuitry of an IC generally provides 5-10 times more I/Os than the traditional method of restricting pads to the periphery. This approach also minimizes overall die size. In this paper we describe the development of a new area-array pad router which differs from other approaches in that no additional metal layer is added (unless needed) and no redistribution is required. We describe the design implementation of this technique and show the results of applying this router on designs requiring 112, 298, 414 and 485 I/Os.

Intrinsic area array ICs: what, why, and how

Area-array bonding technology (i.e. flip-chip, C4) was pioneered by IBM in the late 1960s as an alternative to periphery bonding technology (i.e. wire-bond). In recent years, several commercial companies have started offering bumping and flip-chip services. Flip-chip technology is expected to grow at at compound annual growth rate of 38% through the year 2001. The purpose of this paper is to address the IC design issues and alternatives that are presently being used for area-array bonding technology and show the impact of these design issues at the system level.

Mapping of an automated target recognition application from a graphical software environment to FPGA-based reconfigurable hardware

A significant obstacle to the widespread adoption of FPGA-based configurable computing hardware has been the difficulty of mapping applications onto this hardware. We are developing a software development system called CHAMPION to automate the process of mapping applications in the graphical software environment Khoros to multiple FPGA-based architectures. The work described were consists of the development of requirements for thee library primitives used by CHAMPION and the manual mapping of an automatic target recognition algorithm onto FPGA hardware.

Training IP creators and integrators

Intellectual property (IP) blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time to market which results in increased profits. Alliances of companies have been formed to support an open market for IP and standards are being devised to ensure the quality of this IP. Also, a web-based network has been set up to facilitate the matching of providers and consumers. However, a significant problem still needs be addressed: namely, the widespread training of IP creators and integrators. Universities have been offering courses which involve logic synthesis and simulation using VHDL or Verilog along with verification using FPGAs. Now that standards for IP reuse are being developed, these courses need to require students to develop and integrate IP blocks which are compliant with the desired quality level. In this paper, we describe the procedure that we have begun using at the University of Tennessee to train IP creators and integrators to meet these new challenges. In addition, we propose the widespread adoption of this type of training and the development of an infrastructure to support the dissemination of IP shareware.

Teaching custom integrated circuit design and verification

Custom design of integrated circuits is required for the development of digital standard-cell and bit-slice libraries, analog circuits, and other specialized circuits that are not commercially available. Teaching students the design and verification flow at this physical level is valuable in that it provides the understanding and skills they will need to perform these functions in their subsequent employment. Moreover, experiencing custom design provides an appreciation of the tasks involved for those whose primary job functions will involve synthesis using vendor-supplied libraries. This paper describes the goals, content and experiences of a semester graduate course in which projects are verified not only with simulations but also with measurements on prototypes fabricated via MOSIS. A standard-cell library and test circuitry that are compatible with the Cadence toolset and AMIS-0.6 micron process are described. These are available at no charge to anyone via the world-wide web.