Donald W. Bouldin

A Cluster Separation Measure

A measure is presented which indicates the similarity of clusters which are assumed to have a data density which is a decreasing function of distance from a vector characteristic of the cluster. The measure can be used to infer the appropriateness of data partitions and can therefore be used to compare relative appropriateness of various divisions of the data. The measure does not depend on either the number of clusters analyzed nor the method of partitioning of the data and can be used to guide a cluster seeking algorithm.

Hardware acceleration of pseudo-random number generation for simulation applications

In modeling and simulation tools, random numbers from a variety of probability distribution functions are generated to simulate the behavior of random events. Inefficient generation of these numbers can be a significant bottleneck for simulation applications. Generating these random numbers imprecisely can skew results. An efficient and scalable fixed-point method for generating random numbers for any probability distribution function in a Field Programmable Gate Array (FPGA) is developed. A Pi estimator, a Monte Carlo integrator, and a stochastic simulator for chemical species are developed in software. Estimates are made regarding their potential to be accelerated using the designed FPGA. Results are presented which examine trade-offs between the number of gates used by the FPGA and the accuracy of the random numbers generated. The work shows that generating random numbers using the designed hardware can significantly increase the performance of simulation applications that require many random numbers.

Design for packageability-the impact of bonding technology on the size and layout of VLSI dies

The impact of bonding technology from an IC designers point of view is studied. Work by others has concentrated just on the effect of packaging alone, whereas this study investigates the effect of changing the VLSI dies. Specifically, the impact of wire-bond and flip-chip technologies on the size and layout of VLSI dies is demonstrated by means of general discussion and detailed examples. Three VLSI chips of various sizes and I/O requirements have been synthesized based on a standard-cell library for both wire-bond and flip-chip. The results show different die layouts and sizes can be achieved based on the choice of wire-bond or flip-chip technologies.<<ETX>>

Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems

Adaptive computing systems (ACSs) can serve as flexible hardware accelerators for applications in domains such as image and digital signal processing. However, the mapping of applications onto ACSs using the traditional methods can take months for a hardware engineer to develop and debug. To enable application designers to map their applications automatically onto ACSs, a software design environment called CHAMPION was developed at the University of Tennessee. This environment permits high-level design entry using the Cantata graphical programming environment from KRI and hides from the user the low-level details of the hardware architecture. Thus, ACSs can be utilized by a wider audience and application development can be accomplished in less time. Furthermore, CHAMPION provides the means to map onto multiple ACS platforms, thereby exploiting rapid advances being made in hardware.

Impact of packaging technology on system partitioning: a case study

This paper emphasizes concurrent consideration of the partitioning of a microelectronic circuit design into multiple dies and the selection of the appropriate packaging technology for implementation of the entire system. Partitioning a large design into a multichip package is a non-trivial task. Similarly, selection of the MCM packaging technology to accommodate a multichip solution can also be puzzling. The interdependencies of these two problems afford the opportunity to achieve a global optimum when considered concurrently. In this paper we address the partitioning/MCM technology tradeoff, their interdependency and previous work in this area. The SUN MicroSparc CPU is used as a demonstration vehicle and is partitioned for different MCM technologies. The preliminary results show that the optimum number of partitions and contents of each partition depend heavily on the choice of MCM technologies for a given application.

Design for packageability-early consideration of packaging from a VLSI designer's viewpoint

Designing VLSI dies without considering packaging issues may result in a suboptimum system. It is argued that before the design of VLSI dies is completed, packaging issues should be evaluated, since they may affect choices in VLSI circuit design and layout. To illustrate this, the design of an image processing chip-set of three integrated circuits for wire-bond printed circuit board (PCB) and flip-chip multichip module deposited (MCM-D) technologies is reviewed. It is shown that the characteristics of these chips vary, since they are designed with different packaging in mind.<<ETX>>

Parallel architecture for OPS5

An architecture that captures some of the inherent parallelism of the OPS5 expert system language has been designed and implemented at Oak Ridge National Laboratory. A central feature of this architecture is a network bus over which a single host processor broadcasts messages to a set of parallel rule processors. This transmit-only bus is implemented by a memory-mapped scheme which permits the rule processors to be decoded in parallel. All OPS5 rule matching processes and most of the processes associated with conflict resolution are executed by the parallel rule processors. The host performs the tasks associated with the firing of a rule selected by the conflict resolution process. Performance data are presented for the prototype system which comprises a host processor and 64 parallel rule processors, each embodying a Motorola MC68000 microprocessor and 512 Kbytes of unshared memory.

Improved Unitary and Multicomponent Gaseous Insulators

Improved unitary and multicomponent gaseous insulators are systematically designed according to detailed knowledge of fundamental electron-molecule interactions. Knowledge of the electron attachment and electron slowing-down properties of dielectric gases/mixtures as functions of electron energy is shown to be especially significant. On the basis of such knowledge it is possible to improve the gaseous dielectrics breakdown strength by effectively controlling the numbers and energies of the electrons present. Several unitary (e.g., C<inf>4</inf>+F<inf>6</inf>, c-C<inf>4</inf>F6, and iso-C<inf>4</inf>F<inf>6</inf>) and multicomponent (e.g., C<inf>4</inf>F<inf>6</inf>/SF<inf>6</inf>/N<inf>2</inf> and c-C<inf>4+</inf>F<inf>8</inf>/C<inf>4+</inf>F<inf>6</inf>/SF<inf>6</inf>/N<inf>2</inf>) gaseous systems have been tested and found to have better DC breakdown strength properties than SF<inf>6</inf>. These findings are reported and discussed.

Early cost/performance cache analysis of a split MCM-based MicroSparc CPU

Optimization of a microelectronic system is a difficult task involving a number of different disciplines. Often, an optimization in one discipline will result in a sub-optimal solution in other areas and the overall system. This paper looks into the optimization of a microelectronics system by concurrent consideration of the micro-architecture, package, and logic partitioning. This approach will attempt to identify an optimized design by helping the designer to explore the multi-dimensional solution space and evaluate the design candidates based on their system-level cost/performance. As a demonstration vehicle, we have evaluated the SUN MicroSparc CPU for possible MCM packaging based on sets of smaller dies using this approach. Cost/performance figure-of-merits are presented for various cache sizes using cost-optimized partitioning for flip-chip MCM-D packaging.

Design implementation of intrinsic area array ICs

Arranging I/O in a matrix array over the core circuitry of an IC generally provides 5-10 times more I/O than the traditional method of restricting pads to the periphery. This approach also minimizes overall die size. This method was pioneered by IBM over thirty years ago and has recently become attractive for new designs requiring several hundred I/O. In this paper we describe the development of a new area-array pad router which differs from other approaches in that no additional metal layer is added (unless needed) and no redistribution is required. We describe the design guideline definition, data preparation, pad placement, pad assignment, pad routing, and output padframe generation of this technique. The results of applying this router are shown for sample designs requiring 112, 298 and 485 I/Os.