Peyman Dehkordi

Design for packageability-the impact of bonding technology on the size and layout of VLSI dies

The impact of bonding technology from an IC designers point of view is studied. Work by others has concentrated just on the effect of packaging alone, whereas this study investigates the effect of changing the VLSI dies. Specifically, the impact of wire-bond and flip-chip technologies on the size and layout of VLSI dies is demonstrated by means of general discussion and detailed examples. Three VLSI chips of various sizes and I/O requirements have been synthesized based on a standard-cell library for both wire-bond and flip-chip. The results show different die layouts and sizes can be achieved based on the choice of wire-bond or flip-chip technologies.<<ETX>>

Impact of packaging technology on system partitioning: a case study

This paper emphasizes concurrent consideration of the partitioning of a microelectronic circuit design into multiple dies and the selection of the appropriate packaging technology for implementation of the entire system. Partitioning a large design into a multichip package is a non-trivial task. Similarly, selection of the MCM packaging technology to accommodate a multichip solution can also be puzzling. The interdependencies of these two problems afford the opportunity to achieve a global optimum when considered concurrently. In this paper we address the partitioning/MCM technology tradeoff, their interdependency and previous work in this area. The SUN MicroSparc CPU is used as a demonstration vehicle and is partitioned for different MCM technologies. The preliminary results show that the optimum number of partitions and contents of each partition depend heavily on the choice of MCM technologies for a given application.

Design for packageability-early consideration of packaging from a VLSI designer's viewpoint

Designing VLSI dies without considering packaging issues may result in a suboptimum system. It is argued that before the design of VLSI dies is completed, packaging issues should be evaluated, since they may affect choices in VLSI circuit design and layout. To illustrate this, the design of an image processing chip-set of three integrated circuits for wire-bond printed circuit board (PCB) and flip-chip multichip module deposited (MCM-D) technologies is reviewed. It is shown that the characteristics of these chips vary, since they are designed with different packaging in mind.<<ETX>>

Early cost/performance cache analysis of a split MCM-based MicroSparc CPU

Optimization of a microelectronic system is a difficult task involving a number of different disciplines. Often, an optimization in one discipline will result in a sub-optimal solution in other areas and the overall system. This paper looks into the optimization of a microelectronics system by concurrent consideration of the micro-architecture, package, and logic partitioning. This approach will attempt to identify an optimized design by helping the designer to explore the multi-dimensional solution space and evaluate the design candidates based on their system-level cost/performance. As a demonstration vehicle, we have evaluated the SUN MicroSparc CPU for possible MCM packaging based on sets of smaller dies using this approach. Cost/performance figure-of-merits are presented for various cache sizes using cost-optimized partitioning for flip-chip MCM-D packaging.

Design implementation of intrinsic area array ICs

Arranging I/O in a matrix array over the core circuitry of an IC generally provides 5-10 times more I/O than the traditional method of restricting pads to the periphery. This approach also minimizes overall die size. This method was pioneered by IBM over thirty years ago and has recently become attractive for new designs requiring several hundred I/O. In this paper we describe the development of a new area-array pad router which differs from other approaches in that no additional metal layer is added (unless needed) and no redistribution is required. We describe the design guideline definition, data preparation, pad placement, pad assignment, pad routing, and output padframe generation of this technique. The results of applying this router are shown for sample designs requiring 112, 298 and 485 I/Os.

An intrinsic area-array pad router for ICs

Arranging I/Os in a matrix array over the core circuitry of an IC generally provides 5-10 times more I/Os than the traditional method of restricting pads to the periphery. This approach also minimizes overall die size. In this paper we describe the development of a new area-array pad router which differs from other approaches in that no additional metal layer is added (unless needed) and no redistribution is required. We describe the design implementation of this technique and show the results of applying this router on designs requiring 112, 298, 414 and 485 I/Os.

Intrinsic area array ICs: what, why, and how

Area-array bonding technology (i.e. flip-chip, C4) was pioneered by IBM in the late 1960s as an alternative to periphery bonding technology (i.e. wire-bond). In recent years, several commercial companies have started offering bumping and flip-chip services. Flip-chip technology is expected to grow at at compound annual growth rate of 38% through the year 2001. The purpose of this paper is to address the IC design issues and alternatives that are presently being used for area-array bonding technology and show the impact of these design issues at the system level.

Development of a DSP/MCM subsystem assessing low-volume, low-cost MCM prototyping for universities

This paper discusses the design and development of a general-purpose programmable DSP subsystem packaged in a multichip module. The subsystem contains a 32-bit floating-point programmable DSP processor along with 256 K-byte of SRAM; 128 K-byte of FLASH memory, 10 K-gate FPGA and a 6-channel 12-bit ADC. The complete subsystem is interconnected on a 37 mm by 37 mm MCM-D substrate and packaged in a 320-pin ceramic quad flat pack. The design has been submitted to the MIDAS brokerage service to be fabricated by Micro Module Systems. Our experience shows that low-volume MCM prototyping is achievable and somewhat affordable for universities. The design flow electrical and thermal analyses, CAD tools, cost and lessons learned are discussed in this paper.

Determination of area-array bond pitch for optimum MCM systems: a case study

Microelectronics system designers need to understand and evaluate the impact of advanced packaging parameters which have become an integral part of microelectronics systems. This paper evaluates the impact of bond pitch for a flipchip multichip system through a case study. The SUN MicroSparc CPU was used as a representative of a large design where the design has to be partitioned and interconnected using MCM technology. Early analysis techniques were used to analyze the design for various pitches ranging from 150 to 400 micron in 50 micron increments. Results suggest that various bond pitches affect the system cost/performance and there is a minimum pitch at which lowering the pitch will degrade the cost/performance metrics.

Enhancement of MCM testability using an embedded reconfigurable FPGA

The testability of an MCM can be enhanced significantly for very little cost whenever a reprogrammable FPGA component that is already embedded in the MCM for functionality is utilized for diagnostics. This approach can have some of the characteristics of a smart substrate which uses the scan cell beside-the-signal-path (BSP) methodology. The design and implementation of an MCM with this capability is presented along with descriptions of the self-test algorithms, fault isolation and real-time testing and monitoring that this method provides.