Chang-Ho Tseng

Low RF loss and noise of transmission lines on Si substrates using an improved ion implantation process

Very low power loss /spl les/0.6 dB at 110 GHz and noise of <0.25 dB at 18 GHz have been measured on transmission lines fabricated on Si substrates and implanted with protons. In contrast, a much worse power loss of 5 dB and higher noise of 2.5 dB were measured without implantation. This large improvement arises from the high resistivity by proton implantation, which was also done after forming the transmission lines and at a reduced energy of /spl sim/ 4 MeV for easier process integration into current VLSI technology.

A novel laser-processed self-aligned gate-overlapped LDD poly-Si TFT

A novel process for fabricating self-aligned gate-overlapped LDD (SAGOLDD) poly-Si thin film transistors (TFTs) was demonstrated. Laser irradiation for dopant activation was performed from the backside of the quartz wafer. The graded LDD structure was naturally formed under the gate edges due to the lateral diffusion of the dopants during the laser activation. In comparison with the conventional laser-processed self-aligned poly-Si TFTs, the SAGOLDD poly-Si TFTs exhibited lower leakage current, suppressed kink effect, and higher reliability. Moreover, the proposed process was simple and very suitable for low-temperature processing.

Investigation of inductively coupled plasma gate oxide on low temperature polycrystalline-silicon TFTs

By optimizing the inductively coupled plasma (ICP) oxidation condition, a thin oxide of 10 nm has been grown at 350/spl deg/C to achieve excellent gate oxide integrity of low leakage current<5/spl times/10/sup -8/ A/cm/sup 2/ (at 8 MV/cm), high breakdown field of 9.3 MV/cm and low interface trap density of 1.5/spl times/10/sup 11/ /eV cm/sup 2/. The superior performance poly-Si TFTs using such a thin ICP oxide were attained to achieve a high ON current of 110 /spl mu/A//spl mu/m at V/sub D/=1 V and V/sub G/=5 V and the high electron field effect mobility of 231 cm/sup 2//V/spl middot/S.

Study on dopant activation of phosphorous implanted polycrystalline silicon thin films by KrF excimer laser annealing

Abstract The KrF excimer laser annealing of phosphorous implanted polycrystalline silicon (poly-Si) films had been investigated completely. Resistors were fabricated to measure sheet resistance of poly-Si film. The interference effect, heat absorption of capping oxide as well as transformation of poly-Si grain size during laser annealing were reported. Depending on the carrier concentrations, poly-Si exhibits different sheet resistance behavior when the excimer laser fluence is higher than the full-melt threshold fluence. The sheet resistance of poly-Si film has an abnormal increase from 5×104 to 4×10 6 Ω/□ when the excimer laser energy is higher than full-melt threshold energy.

Fabrication of low-temperature poly-Si thin film transistors with self-aligned graded lightly doped drain structure

A novel approach for fabricating low-temperature poly-Si (LTPS) thin film transistors (TFTs) with self-aligned graded lightly doped drain (LDD) structure was demonstrated. The self-aligned graded LDD structure was formed by side-etching the Al gate under the photoresist followed by excimer laser irradiation for dopant activation and lateral diffusion. The graded LDD poly-Si TFTs exhibited low-leakage-current characteristics without significantly sacrificing driving capability due to the graded dopant distribution in the LDD regions, in which the drain electric field could be reduced. The leakage current of 1 μm graded LDD LTPS TFTs at Vds = 5 V and Vgs = -10 V could reach below 1 pA/μm, and the on/off current ratio at Vds = 5 V exceeded 10 7 .

A novel germanium doping method for fabrication of high-performance p-channel poly-Si 1-x Ge x TFT by excimer laser crystallization

In this letter, a novel process for fabricating p-channel poly-Si/sub 1-x/Ge/sub x/ thin-film transistors (TFTs) with high-hole mobility was demonstrated. Germanium (Ge) atoms were incorporated into poly-Si by excimer laser irradiation of a-Si/sub 1-x/Ge/sub x//poly-Si double layer. For small size TFTs, especially when channel width/length (W/L) was less than 2 /spl mu/m/2 /spl mu/m, the hole mobility of poly-Si/sub 1-x/Ge/sub x/ TFTs was superior to that of poly-Si TFTs. It was inferred that the degree of mobility enhancement by Ge incorporation was beyond that of mobility degradation by defect trap generation when TFT size was shrunk to 2 /spl mu/m/2 /spl mu/m. The poly-Si/sub 0.91/Ge/sub 0.09/ TFT exhibited a high-hole mobility of 112 cm/sup 2//V-s, while the hole mobility of the poly-Si counterpart was 73 cm/sup 2//V-s.

Effect of Temperature and Illumination on the Instability of a-Si:H Thin-Film Transistors under AC Gate Bias Stress

This work investigates the temperature and illumination effects on the a-Si:H thin-film transistors (a-SiH TFTs) under AC gate bias stress to find the larger threshold voltage shift and subthreshold swing change for the bias-temperature-stress (BTS) and bias-illumination-stress (BIS). Excess carriers from thermal-generation electron-hole pairs or photoexcited electron-hole pairs may significantly influence the instability of a-Si:H TFTs during bias stress. The instability mechanisms originate from the carrier-induced defect creation enhanced by thermal generation in the BTS case and also emphasized by photoexcitation for the BIS case. Both stress conditions will induce a larger threshold voltage shift and higher cutoff frequency than those for simple bias stresses.

Thickness Dependence of Microstructure of Laterally Crystallized Poly-Si Thin Films and Electrical Characteristics of Low-Temperature Poly-Si TFTs

The effects of thickness of a-Si thin films on the resulting microstructure of metal-induced laterally crystallized (MILC) poly-Si and electrical characteristics of MILC low temperature poly-Si (LTPS) thin film transistors (TFTs) were investigated. The TEM images revealed a double-layer structure in the 1000-A MILC poly-Si thin film. However, for the 400-A MILC poly-Si thin film, there were single-layer grains within the thin film layer. The reason has been ascribed to the geometry restriction in the crystallization procedure. The average mobility of fabricated MILC LTPS TFTs with active layer thickness of 400 A showed a little higher than that with 1000 A active layer. Moreover, the MILC LTPS TFTs with active layer thickness of 400 A exhibited better electrical uniformity than those with 1000 A active layer either in threshold voltage or field-effect mobility. The reason should also be attributed to the different crystalline structures within the two thin-film layers.

An Investigation of Bias Temperature Instability in Hydrogenated Low-Temperature Polycrystalline Silicon Thin Film Transistors

The instability mechanisms of the hydrogenated n-channel low-temperature polycrystalline silicon thin film transistors under on-state stress were investigated with various bias stress conditions and device channel widths. It was found that hot carrier degradation which originated from a high drain electric field and self-heating during high current operation were the two dominant mechanisms responsible for device degradation. An electrically reversible depassivation/passivation phenomenon was also found in devices under high current stress, but not in those under hot carrier stress. It was inferred that the self-heating effect would accelerate the bond breakage and diffusion of hydrogen ions, thus enhancing the rate of depassivation/passivation. Moreover, when the current in the hot carrier stress mode was sufficiently high, self-heating became the dominant degradation mechanism and hot carrier degradation phenomenon was also suppressed for devices with large channel width. Meanwhile, the electrically reversible depassivation/passivation phenomenon also occurred in this case.

Symmetric Gate-Overlapped LDD Poly-Si TFTs with Selective and Isotropic Deposited Ni Sub-gate

A novel fabrication process for self-aligned gate-overlapped lightly doped drain (SAGOLDD) thin-film transistors (TFTs) using excimer laser irradiation to form the graded LDD dopant profile and selectively plated Ni surrounding-gate to form the gate-overlap is demonstrated. The SAGOLDD TFT device exhibits much lower leakage current, higher on/off current ratio and better hot carrier stress endurance than self-aligned (SA) TFTs due to the lower electric field generated by graded LDD dopant profile.