Chang-Kyung Seong

A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms

As the data rate requirements for many wireline applications increase, channel bandwidth limitation becomes a critical problem in serial interfaces. Equalizers are often used as a solution for this problem. In addition, many applications require the equalizer to be adaptive so that it can provide optimized equalization for different channel conditions. Various types of adaptive equalizers have been investigated for high-speed serial interface applications [1–6]. In the spectrum-balancing method, adaptive equalization is achieved by comparing high and low frequency components of signal power and generating feedback signals until the power spectrum is balanced [1]. Unfortunately, the precision of this scheme is easily affected by process variations, and capacitors both in filters and the feedback loop occupy a large Si area. Digital-signal processing based on maximum likelihood sequence detection can be used for adaptive equalization [2]. But, speed limitation and architecture complexity of ADC limits applicability of this scheme in high-speed applications. In the eye-opening monitoring (EOM) scheme, quality of the signal eye diagram is measured and used for equalizer adaptation [3–6]. For this method, a clock-recovery circuit is needed in order to generate clock signals synchronized to data for sampling. However, it can be difficult to recover clock signals from the initially closed eye diagram, limiting the applicability of this scheme. In this paper, we demonstrate an adaptive equalizer based on asynchronous-sampling histograms.

A 5.4-Gbit/s Adaptive Continuous-Time Linear Equalizer Using Asynchronous Undersampling Histograms

We demonstrate a new type of adaptive continuous-time linear equalizer (CTLE) based on asynchronous undersampling histograms. Our CTLE automatically selects the optimal equalizing filter coefficient among several predetermined values by searching for the coefficient that produces the largest peak value in histograms obtained with asynchronous undersampling. This scheme is simple and robust and does not require clock synchronization for its operation. A prototype chip realized in 0.13-μm CMOS technology successfully achieves equalization for 5.4-Gbit/s 231 - 1 pseudorandom bit sequence data through 40-, 80-, and 120-cm PCB traces and 3-m DisplayPort cable. In addition, we present the results of statistical analysis with which we verify the reliability of our scheme for various sample sizes. The results of this analysis are confirmed with experimental data.

A 10-Gb/s Adaptive Look-Ahead Decision Feedback Equalizer With an Eye-Opening Monitor

We demonstrate a novel adaptive look-ahead decision feedback equalizer (LADFE) that uses the measured eye diagram for equalization adaptation and verification. The eye diagram is obtained with a new type of eye-opening monitor (EOM), which measures the magnitude of the received signals having different data patterns and, using this, estimates intersymbol interference and determines the amount of adaptation needed for the LADFE. A 10-Gb/s adaptive two-tap LADFE with an EOM is fabricated in 90-nm CMOS technology. The eye diagrams for equalized signals are successfully obtained, and adaptation of the LADFE is achieved for PCB channels up to 40 cm. The LADFE core occupies and consumes 11 mW at 1.2-V supply voltage.

Clock and Data Recovery Circuit Using Digital Phase Aligner and Phase Interpolator

Clock and data recovery circuit using digital phase aligner and phase interpolator is proposed for multi-channel link applications. The proposed circuit reduces recovered clock jitter and alleviates the problem of distorted clock duty cycle. It is realized in 0.13um CMOS technology. Its power dissipation is 9.7mW at 1.2V power supply and its occupation area is 290×230um2 with multi-phase clock generation block. The experimental results show that the proposed circuit recovers 1Gb/s of 27-1 PRBS with no error.

A New Network Synchronizer Using Phase Adjustment and Feedforward Filtering Based on Low-Cost Crystal Oscillators

A new network synchronizer using a two-way message exchange is proposed and implemented in a field-programmable gate array (FPGA). This synchronizer aligns its clock signal and time of day to that of the master node. For high-precision frequency control, a new phase adjustment method is employed, which efficiently provides high-frequency resolution and deterministic frequency control gain. In addition, a feedforward filter is used to reduce dithering of the time offset due to quantization errors in time-stamping. Even with a low-cost crystal oscillator, successful synchronization with root-mean-square (RMS) jitters of 0.1856 unit interval is achieved.

A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution

This paper describes a 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with a 256-level phase resolution using only 4-phase reference clock. A novel scheme is proposed to enhance the phase resolution with little additional power consumption and chip area. A digitally-controlled delay buffer having a variable delay tunes output phase finely for a higher resolution. A prototype chip was fabricated with 0.18 mum CMOS technology. In the measurement, the CDR has plusmn400ppm frequency offset tolerance and a flat jitter performance for wide variations of delay buffer. The power consumption of the CDR core is 17.8mW with 1.8V supply and the core occupies 255 mum times 165mum

A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator

We propose a new Clock and Data Recovery (CDR) circuit for burst-mode applications. It can recover clock signals after two data transitions and endure long sequence of consecutive identical digits. Two Digital Phase Aligners (DPAs), triggered by rising or falling edges of input data, recover clock signals, which are then combined by a phase interpolator. This configuration reduces the RMS jitters of the recovered clock by 30% and doubles the maximum run length compared to a previously reported DPA CDR. A prototype chip is demonstrated with 0.18-μm CMOS technology. Measurement results show that the chip operates without any bit error for 1.25-Gb/s 231-1 PRBS with 200-ppm frequency offset and recovers clock and data after two clock cycles.