Myung-Jae Lee

Si avalanche photodetectors fabricated in standard complementary metal-oxide-semiconductor process

The authors report silicon avalanche photodetectors (APDs) fabricated with 0.18μm standard complementary metal-oxide-semiconductor (CMOS) process without any process modification or a special substrate. When the bias is above the avalanche breakdown voltage, CMOS-compatible APD (CMOS-APD) exhibits negative photoconductance in photocurrent-voltage relationship and rf peaking in the photodetection frequency response. The reflection coefficient measurement of CMOS-APD indicates that rf peaking is due to resonance caused by appearance of inductive components in avalanche region. The rf-peaking frequency increases with the increasing reverse bias voltage.

10-Gb/s 850-nm CMOS OEIC Receiver With a Silicon Avalanche Photodetector

We present a 10-Gb/s optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.13-μm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. The OEIC receiver consists of a CMOS-compatible avalanche photodetector (CMOS-APD), a transimpedance amplifier (TIA), an offset cancellation network, a variable equalizer (EQ), a limiting amplifier (LA), and an output buffer. The CMOS-APD provides high responsivity as well as large photodetection bandwidth. The TIA is composed of two-stage differential amplifiers with high feedback resistance of 4 kΩ. The EQ compensates high-frequency loss by controlling the boosting gain with a capacitor array. The LA consists of five-stage gain cells with active feedback and negative capacitance to achieve broadband performance. With the OEIC receiver, we successfully demonstrate transmission of 10-Gb/s optical data at 850 nm with a bit error rate of 10-12 at the incident optical power of -4 dBm. The OEIC receiver has the core chip area of about 0.26 mm2 and consumes about 66.8 mW.

A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain-bandwidth product

We present a silicon avalanche photodetector (APD) fabricated with standard complementary metal-oxide-semiconductor (CMOS) technology without any process modification or special substrates. The CMOS-APD is based on N+/P-well junction, and its current-voltage characteristics, responsivity, avalanche gain, and photodetection frequency response are measured. Gain-bandwidth product over 1 THz is achieved with the CMOS-APD having avalanche gain of 569 and 3-dB photodetection bandwidth of 3.2 GHz.

Association of fatty acid composition in serum phospholipids with metabolic syndrome and arterial stiffness.

BACKGROUND AND AIM We examined the association of fatty acid (FA) composition in serum phospholipids with the features of metabolic syndrome (MetS) and arterial stiffness. METHODS Korean men (n = 593, 30-79 yrs) were categorized based on the number of MetS risk factors (RFs) and measured for the markers of MetS, serum phospholipid FA composition and brachial-ankle pulse wave velocity (baPWV), an index for the severity of arterial stiffness. RESULTS Insulin resistance (HOMA-IR), baPWV, LDL size, and adiponectin were significantly altered corresponding to the number of MetS RFs. The proportions of total monounsaturated FA, palmitoleic acid (16:1), oleic acid (18:1ω-9) and dihomo-γ-linolenic acid (DGLA, 20:3ω-6) in serum phospholipids, and DGLA/linoleic acid (LA) (20:3ω-6/18:2ω-6), deta9-desaturase activity (D9D-16: 16:1/16:0 and D9D-18: 18:1ω-9/18:0) significantly increased corresponding to the number of MetS RFs, but D5D (20:4ω-6/20:3ω-6) decreased. baPWV positively correlated with HOMA-IR, palmitic acid (16:0), oleic acid, D6D (18:3ω-6/18:2ω-6), DGLA/LA and D9D-18, and negatively with adiponectin, LDL size, LA, docosahexaenoic acid (DHA, 22:6ω-3) and D5D. Multiple stepwise regression models revealed that baPWV was significantly influenced by systolic blood pressure, age, body weight, triglyceride and LA in serum phospholipids (R(2) = 0.378). Interestingly, baPWV (1419 ± 1 cm/s) and MetS (22%) were highest in individuals with lower proportion of LA (< 12.361%) and higher proportion of DGLA (≥ 1.412%) in serum phospholipid FAs. CONCLUSION The features of MetS significantly related to serum phosopholipid FA composition. Particularly, arterial stiffness was associated with LA additively together with DLGA. It may suggest a potential benefit of sufficient amounts of LA in serum or in diet can reduce cardiovascular risk.

Effects of Guard-Ring Structures on the Performance of Silicon Avalanche Photodetectors Fabricated With Standard CMOS Technology

We investigate the effects of guard-ring (GR) structures on the performance of silicon avalanche photodetectors (APDs) fabricated with the standard complementary metal-oxide-semiconductor (CMOS) technology. Four types of CMOS-compatible APDs (CMOS-APDs) based on the p+/ n-well junction with different GR structures are fabricated, and their electric-field profiles are simulated and analyzed. Current characteristics, responsivity, avalanche gain, and photodetection bandwidth for CMOS-APDs are measured and compared. It is demonstrated that the GR realized with shallow trench isolation provides the best CMOS-APD performance.

Area-Dependent Photodetection Frequency Response Characterization of Silicon Avalanche Photodetectors Fabricated With Standard CMOS Technology

We investigate the area-dependent characteristics of photodetection frequency responses of 850-nm silicon avalanche photodetectors (APDs) fabricated with standard complementary metal-oxide-semiconductor (CMOS) technology. CMOS-compatible APDs (CMOS-APDs) based on a p+/n-well junction with four different device areas are used for the investigation, and we identify factors that influence photodetection frequency responses with the goal of achieving optimal photodetection bandwidth performance. Their current-voltage characteristics, electrical reflection coefficients, and photodetection frequency responses are measured, and the characteristics of the CMOS-APD photodetection frequency responses are analyzed using equivalent circuit models. From this, it is clarified how the four different factors of photogenerated-carrier transit time, device RC time constant, inductive-peaking effect, and parasitics contribute to the photodetection frequency responses and how their contribution changes with device areas. Among the four types of CMOS-APDs investigated in this study, the 10 × 10 μm2 CMOS-APD has the largest 3-dB photodetection bandwidth of 7.6 GHz.

Equivalent Circuit Model for Si Avalanche Photodetectors Fabricated in Standard CMOS Process

We present an equivalent circuit model for CMOS-compatible avalanche photodetectors. The equivalent circuit model includes an inductive component for avalanche delay, a current source for photogenerated carriers, and several components that model the device structure and parasitic effects. The model provides accurate impedance characteristics and photodetection frequency responses.

High-Speed CMOS Integrated Optical Receiver With an Avalanche Photodetector

We present a high-speed monolithically integrated optical receiver fabricated with 0.13-mum standard complementary metal-oxide-semiconductor (CMOS) technology. The optical receiver consists of a CMOS-compatible avalanche photodetector (CMOS-APD) and a transimpedance amplifier (TIA). The CMOS-APD provides high responsivity as well as large bandwidth. Its bandwidth is further enhanced by the TIA having negative capacitance, which compensates undesired parasitic capacitance. With the CMOS integrated optical receiver, 4.25-Gb/s optical data are successfully transmitted with a bit-error rate less than 10-12 at the incident optical power of - 5.5 dBm.

An integrated 12.5-Gb/s optoelectronic receiver with a silicon avalanche photodetector in standard SiGe BiCMOS technology.

An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 2(31)-1 pseudorandom bit sequence optical data with the bit-error rate less than 10(-12) at incident optical power of -7 dBm. The OEIC core has 1000 μm x 280 μm chip area, and consumes 59 mW from 2.5-V supply. To the best of our knowledge, this OEIC receiver achieves the highest data rate with the smallest sensitivity as well as the best power efficiency among integrated OEIC receivers fabricated with standard Si technology.

SNR characteristics of 850-nm OEIC receiver with a silicon avalanche photodetector

We investigate signal-to-noise ratio (SNR) characteristics of an 850-nm optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The OEIC receiver is composed of a Si avalanche photodetector (APD) and BiCMOS analog circuits including a transimpedance amplifier with DC-balanced buffer, a tunable equalizer, a limiting amplifier, and an output buffer with 50-Ω loads. We measure APD SNR characteristics dependence on the reverse bias voltage as well as BiCMOS circuit noise characteristics. From these, we determine the SNR characteristics of the entire OEIC receiver, and finally, the results are verified with bit-error rate measurement.