Jinsoo Rhim

A 5-Gb/s low-power transmitter with voltage-mode output driver in 90nm CMOS technology

A 5-Gb/s low-power transmitter having an output impedance calibration circuit and a voltage-mode output driver is implemented for high-speed serial link applications. The output impedance calibration circuit matches the output impedance of output driver to the characteristic impedance of the channel. This transmitter includes 32:1 serializer based on voltage-mode logic which operates successfully at 5-Gb/s. In addition, on-chip parallel PRBS7 (27−1) generator is implemented for testing. The transmitter consumes 8.6mW with 300mVp-p output swing and occupies 60 μm × 70 μm of area.

Verilog-A behavioral model for resonance-modulated silicon micro-ring modulator

We present an accurate behavior model for Si micro-ring modulators (MRM) based on Verilog-A, a standard simulation tool for electronic system design. Our model describes the electrical characteristics of the Si MRM using an equivalent circuit and the optical characteristics based on the couple-mode theory. The accuracy of our model is confirmed by comparing simulation results of our behavior model with the measurement results of a fabricated Si MRM. With this behavior model, co-simulation of Si MRM and electronic driving circuits in the standard electronic design environment can be easily performed.

A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology

This paper reports a 10-Gb/s power and area efficient clock and data recovery circuit implemented in 65-nm CMOS technology. CMOS static circuits are used as much as possible so that the power consumption and the chip area can be minimized. In order to alleviate the supply sensitivity of CMOS static circuits, a supply-regulator is implemented. At 10-Gb/s, the clock and data recovery circuit consumes 5-mW of power and occupies 0.0075mm2 of area.

Parametric Characterization of Self-Heating in Depletion-Type Si Micro-Ring Modulators

The influence of self-heating on the static transmission characteristics of depletion-type Si micro-ring modulators (MRMs) is investigated. Self-heating, caused by free-carrier absorption of the input light inside the doped ring waveguide, increases the effective refractive index of the ring waveguide and results in the red-shifted resonance wavelength. This phenomenon is modeled based on the coupled-mode equation with a newly-introduced self-heating coefficient R. The accuracy of our model is confirmed by measurement. In addition, dependence of R on device size and doping concentration is experimentally investigated and the resulting dependence is explained.

A 10-Gb/s Adaptive Look-Ahead Decision Feedback Equalizer With an Eye-Opening Monitor

We demonstrate a novel adaptive look-ahead decision feedback equalizer (LADFE) that uses the measured eye diagram for equalization adaptation and verification. The eye diagram is obtained with a new type of eye-opening monitor (EOM), which measures the magnitude of the received signals having different data patterns and, using this, estimates intersymbol interference and determines the amount of adaptation needed for the LADFE. A 10-Gb/s adaptive two-tap LADFE with an EOM is fabricated in 90-nm CMOS technology. The eye diagrams for equalized signals are successfully obtained, and adaptation of the LADFE is achieved for PCB channels up to 40 cm. The LADFE core occupies and consumes 11 mW at 1.2-V supply voltage.

A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO

A low-voltage phase-locked-loop (PLL) circuit with a supply-noise-compensated feedforward ring voltage-controlled oscillator (FRVCO) is demonstrated. The oscillation frequency fluctuation due to supply noise is compensated by adjusting the ratio of driving strength in feedforward and direct paths in FRVCO. A prototype 400-MHz PLL circuit operating at 0.65 V is fabricated with 180-nm standard CMOS process. Measurement results show that supply-noise compensation is successfully achieved. Our PLL consumes only 242.1 μW.

Modeling of self-heating effect for depletion-type Si micro-ring modulator

We present an accurate model for self-heating effect in depletion-type Si micro-ring modulator which describes incident-power dependent transmission and dynamics. Its accuracy is confirmed with measurement. It can be useful for determining optimal modulation conditions.

A Linear Equivalent Circuit Model for Depletion-Type Silicon Microring Modulators

We present a linear equivalent circuit model for the depletion-type Si microring modulator (MRM). Our model consists of three blocks: one for parasitic components due to interconnects and pads, one for the electrical elements of the core p-n junction, and the third for a lossy LC tank representing Si MRM optical modulation characteristics. Model parameter values are extracted from measurement of a fabricated Si MRM device. Simulated modulation characteristics with our equivalent circuit show very good agreement with measured results. Using our model, we can analyze Si MRM modulation frequency response characteristics and perform gain-bandwidth product optimization of the entire Si photonic transmitter composed of a Si MRM and electrical driver circuits.

Modulation performance optimization for depletion-type silicon micro-ring modulators

We demonstrate the technique of determining Si micro-ring modulator device parameters for achieving optimal modulation performance. Our technique is based on a simple analytic equation and confirmed by measurement and numerical solutions. Using this technique, we determine the optimal ring radius for different data rates.

A 10-Gb/s Multiphase Clock and Data Recovery Circuit with a Rotational Bang-Bang Phase Detector

A multiphase clock and data recovery (CDR) circuit having a novel rotational bang-bang phase detector (RBBPD) is demonstrated. The proposed 1/4-rate RBBPD decides the locking point using a single clock phase among sequentially rotating 4 clock phases. With this, our RBBPD has significantly reduced power consumption and chip area. A prototype 10-Gb/s 1/4-rate CDR with RBBPD is successfully realized in 65-nm CMOS technology. The CDR consumes 5.5 mW from 1-V supply and the clock signal recovered from 2 31 -1 PRBS input data has 0.011-UI rms jitter.