Chang Seo Park

Mechanism of Electron Trapping and Characteristics of Traps in

Electron trapping in high- gate dielectrics under constant voltage stress is investigated. It is suggested that the electron trapping occurs through a two-step process: resonant tunneling of the injected electron into the preexisting defects (fast trapping) and thermally activated migration of trapped electrons to unoccupied traps (slow trapping). Characteristics of the electron traps extracted based on the proposed model are in good agreement with the calculated properties of the negatively charged oxygen vacancies. The model successfully describes low-temperature threshold voltage instability in NMOS transistors with /TiN gate stacks.

\hbox{HfO}_{2}

The effect of flatband-voltage reduction [roll-off (R-O)], which limits fabrication options for obtaining the needed band-edge threshold voltage values in transistors with highly scaled metal/high- k dielectric gate stacks, is discussed. The proposed mechanism causing this R-O phenomenon is suggested to be associated with the generation of positively charged oxygen vacancies in the interfacial SiO2 layer next to the Si substrate. The vacancies in the interfacial layer are induced by oxygen outdiffusing into the overlying high-k dielectric. The model is consistent with the variety of observations of R-O dependence on the electrode and substrate type, high-k dielectric composition and thickness, temperature, etc. The models predictions were experimentally verified.

Gate Stacks

We describe an NMOS band edge solution that uses a metal gate doped with Lanthanide elements to achieve work functions as low as 4.05eV. The capping interlayers used in previous works are no longer necessary, and metal gate implementation became much simpler. Using this electrode, low Vth value and high mobility suitable for high performance devices are achieved at a practical EOT of 8Aring

Origin of the Flatband-Voltage Roll-Off Phenomenon in Metal/High-

For the first time, a novel damage-free neutral beam-assisted atomic etching process has successfully demonstrated the removal of the residual high-k dielectric layer after gate patterning. Due to its neutralized atomic flux and chemical reaction, high etch selectivity is observed to improve device performance and reliability. This process should significantly enhance high-k/metal gate manufacturability.

k

Effects of Gd capping of HfSiON gate dielectric on the characteristics of n metal-oxide-semiconductor field effect transistor (nMOSFET) with TaC gate electrode were investigated. MOSFETs with an in situ deposited Gd/TaC bilayer demonstrated a reduced equivalent oxide thickness, 0.9 nm, and low VTH, 0.25 V, compared with MOSFETs without Gd capping layer. Backside secondary ion mass spectroscopy revealed that Gd atoms were diffused into the high-k gate dielectric and interfacial layer between high-k dielectric and Si substrate. The dipole moment at the high-k/SiO2 interface due to Hf–O and RE–O bonds is used to explain the VTH change.

Gate Stacks

For the first time, we illustrate the importance of process sequence for LaOx capped HfSiON/metal gate on performance, variability, scaling, interface quality and reliability. La diffusion to the high-k/low-k interface controls V_t, as well as strongly affects mobility, N_it and BTI. La diffusion is limited to the Si surface by employing SiON interface layer (IL) mitigating the issues of La-induced mobility degradation and PBTI. Improved V_t tunability, reliability and performance are achieved with optimized process sequence, high-k thickness control, LaOx deposition and SiON (not SiO₂) IL. T_inv=1.15 nm and V_t,lin=0.31 V was obtained while achieving the following attributes: mobility~70%, N_it <5times10¹⁰ cm^-2, DeltaV_t<30 m V within wafer, BTI DeltaV_t <40 m V at 125degC. By optimizing these gate stack factors, we have developed and demonstrated structures for 22 nm node LOP application.

Simplified manufacturable band edge metal gate solution for NMOS without a capping layer

To increase the effective work function of a W∕TiSiN metal gate stack without an equivalent oxide thickness (EOT) increase, we developed a process for high-pressure postmetallization annealing in diluted oxygen ambient. Compared with annealing in an atmospheric pressure, oxygen postmetallization annealing (PMA) in a high-pressure ambient (1–20atm) showed further modulation of the effective work function (4.6–4.8eV) without an EOT increase. These differences can be attributed to total amounts of oxygen supplied to gate stack system. Additionally, the origin of EOT increase after the oxygen PMA was attributed to oxidation of the capping metal.

A novel damage-free high-k etch technique using neutral beam-assisted atomic layer etching (NBALE) for sub-32nm technology node low power metal gate/high-k dielectric CMOSFETs

A mechanism of effective work function change of the Ru oxide metal gate under various anneal conditions has been studied. High temperature annealing was found to result in changing the tetragonal phase of RuO 2 to the hexagonal phase characteristic for Ru metal. By extracting the electrode-dielectric band offset magnitude, it was confirmed that such a change in the stoichiometry of Ru oxide leads to the lower effective work function values of the postanneal Ru oxide/high-k gate stacks. The low temperature oxygen anneal treatment of the high temperature annealed Ru oxide electrode stacks recovers the high work function value by supplying oxygen into the decomposed Ru oxide.

Effects of a Gd capping layer on electrical characteristics of metal-oxide-semiconductor field effect transistors with a TaC gate electrode and a HfSiON gate dielectric

The effects of chlorine plasma treatment on HfSiON gate dielectrics were investigated with respect to device performance and reliability characteristics. The chlorine plasma treatment was performed on atomic layer deposited HfSiON films to remove the residual carbon content. The optimal chlorine plasma treatment is shown to lower gate leakage current density without increasing equivalent oxide thickness of the gate stack. Secondary ion mass spectroscopy depth profiling showed that the carbon residue in HfSiON was reduced by the chlorine plasma treatment. It is demonstrated that an optimized chlorine plasma treatment improves the transistor Ion-Ioff characteristics and reduces negative-bias temperature instability.

Device and reliability improvement of HfSiON+LaOx/metal gate stacks for 22nm node application

Electrical properties of the gate stacks with atomic-layer-deposited HfO2 dielectric on either a HF-last cleaned Si substrate or chemical oxide grown by an O3∕de-ionized water clean have been evaluated. The properties of the oxide layers formed at the interface between the high-k dielectric and the substrate in both types of gate stacks are similar as they exhibit identical equivalent oxide thickness and comparable gate leakage current values. However, the gate stack formed on the HF-last cleaned surface shows higher intrinsic mobility and transient charge trapping, which may be explained by the oxygen deficiency model.