R. Jammy

Band-Engineered Low PMOS V T with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme

Using strained SiGe on Si, the threshold voltage of high k PMOS devices is reduced by as much as 300 mV. The 80 nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high kappa and metal gates for 32 nm node and beyond.

Thermally Stable N-Metal Gate MOSFETs Using La-Incorporated HfSiO Dielectric

We report a thermally stable N-metal process in which surface passivation of HfSiO dielectric using thin layers of La₂O₃, deposited by either MBE or PVD, significantly shifts the metal gate effective work function toward the Si conduction band edge. Well-behaved transistors with L_g down to 70 nm have been fabricated with threshold voltage of 0.25V, mobility up to 92% of the universal SiO₂ mobility, and T_inv ~1.6 nm

An Accurate Lifetime Analysis Methodology Incorporating Governing NBTI Mechanisms in High-k/SiO2 Gate Stacks

Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (DeltaVTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach. It was determined that the interface state generation process contains a fast component most likely associated with the defects in the SiO2 interfacial layer induced by the overlaying high-k film. An intrinsic interface state generation rate obtained by subtracting the fast trapping component is found to be similar to that of the conventional SiO2 dielectric

Mechanism of V fb roll-off with High Work function Metal Gate and Low Temperature Oxygen Incorporation to Achieve PMOS Band Edge Work function

V_fb roll-off phenomena in high work function (WF) metal gate on high-k is successfully explained by progressive oxygen vacancy (V_o ⁺) generation in high-k as bottom oxide scales. Based on this understanding, low temperature O incorporation (LTOI) process has been developed, which reduces PMOS V_t significantly by enriching high-k with O without increasing equivalent oxide thickness (EOT).

Strain additivity in III-V channels for CMOSFETs beyond 22nm technology node

For the first time strain additivity on III-V using prototypical (100) GaAs n- and p-MOSFETs is studied via wafer bending experiments and piezoresistance coefficients are extracted and compared with those for Si and Ge MOSFETs. Further understanding of these results is obtained by using multi-valley conduction band model for n-MOS and performing k.p simulations for p-MOS. For GaAs n-MOSFET, uniaxial tensile stress is shown to enhance performance only for small stresses biaxial tensile stress is shown to be more beneficial. Importantly uniaxial compressive stress is beneficial for GaAs pMOSFETs and the piezoresistance effect is much larger than that seen for Si MOSFETs along the <110> channel direction. This works shows that intrinsic mobility and stress induced mobility enhancement are key knobs for scaling of III-V CMOSFETs.

Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT

For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1 nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4 nm) SiOx interface layer. A secondary mechanism, Ge doping (ges4%) in high-k, possibly by up diffusion, also results in higher leakage. With this understanding, we optimized high-k nitridation reducing O and Ge diffusion to achieve EOT=0.91 nm directly on SiGe with leakage equivalent to bulk Si. High Ion (1.5times Si), and low subthreshold slope (73 mV/dec) are also achieved. This mechanism enables high mobility channel gate dielectric development directly on SiGe without the need for Si cap, simplifying processing and device design.

Simplified manufacturable band edge metal gate solution for NMOS without a capping layer

We describe an NMOS band edge solution that uses a metal gate doped with Lanthanide elements to achieve work functions as low as 4.05eV. The capping interlayers used in previous works are no longer necessary, and metal gate implementation became much simpler. Using this electrode, low Vth value and high mobility suitable for high performance devices are achieved at a practical EOT of 8Aring

The effects of Ge composition and Si cap thickness on hot carrier reliability of Si/Si 1-x Ge x /Si p-MOSFETs with high-K/metal gate

We report on new observations of hot carrier (HC) degradation in strained Si/Si1-xGex(x = 0.2 to 0.5) p-MOSFETs. By using low voltage current-voltage measurement coupled with carrier separation, we are able, for the first time, to easily distinguish the energy distribution of the interface traps. High-K dielectrics on SiGe p-channel show higher interface traps generation located close to conduction band under channel hot carrier stressing and uniform interface trap under drain avalanche hot carrier stressing, both of which can be mitigated by increasing Ge% in the Si/SiGe channel. Detailed study on Si capping layer (les 20 Aring) shows good immunity against Drain Avalanche Hot Carrier but is degraded under Channel Hot Carrier stressing. The results suggest that higher Ge% and thinner Si cap is preferably for hot carrier reliability for low voltage application with 10 yrs lifetime at operating voltage of -0.85 V.

Performance and reliability characteristics of the band edge high-k/metal gate nMOSFETs with La-doped Hf-silicate gate dielectrics

La-doped HfSiO samples showed lower Vth and Igate, which was attributed to the dipole formation at the high-k/SiO2 interface. With increasing SiOx content, significant mobility degradation was observed, most likely due to additional La- related charges in the interfacial layer. La-doped devices demonstrate better immunity in the PBTI test and low charge trapping efficiency compared to the control HfSiO.

Impact of Bottom Interfacial Layer on the Threshold Voltage and Device Reliability of Fluorine Incorporated PMOSFETS with High-K/Metal Gate

The effect of F implantation combined with high quality bottom interfacial layer has been investigated in terms of threshold voltage reduction and improvement of device performance of TaCN/AlN/HfSiOx gate stacks for PMOS application. Threshold voltage becomes more positive as AlN, F implantation, and thermally grown interfacial layer steps are added. It is found that F accumulates near the interface with the Si substrate and the observed Vth shift has been attributed to the passivation of positively charged defects in the dielectric stack and additional negative charge associated with F atoms. Thermally grown interfacial layer combined with F implantation resulted in excellent device parameters and reliability as well as lower PMOS Vth due to inherently lower defect density and defect passivation effect by F atoms.