Chang Zeng

Transmission electron microscopy studies of regrown GaN Ohmic contacts on patterned substrates for metal oxide semiconductor field effect transistor applications

Contact selected area regrowth of GaN was performed by metal organic chemical vapor deposition using a silicon nitride dielectric hard mask to define plasma etched recesses and to define source-drain regions. A low temperature regrowth process at 750–850°C was adopted to limit lateral overgrowth. High resolution electron microscopy images and selected area diffraction confirmed the regrowth selectivity and revealed that the low temperature regrown GaN is epitaxial and has a wurtzite crystal structure. I-V characteristics of the fabricated metal oxidesemiconductor field effect transistor show enhancement mode operation.

Optical spectroscopic analysis of selected area epitaxially regrown n+ gallium nitride

Gallium nitride (GaN) metal-insulator-semiconductor field-effect transistor with regrown by selected area metal organic vapor-phase-epitaxy n+ layer has been analyzed by micro-Raman and microphotoluminescence (micro-PL) spectroscopy. The material properties of the regrown n+ layer and the intrinsic layer in the gate region were extracted by using both spectroscopies. The free-carrier concentration of the regrown GaN layer and the intrinsic layer were determined by line shape analysis of the coupled plasmon-phonon mode to be 4.7×1017 and <3×1016cm−3, respectively. The inefficient substitutions of Ga vacancy (VGa) by Si result in relatively low carrier concentration in the regrown GaN layer. From the shift of E2(2) Raman peak and the near-band-edge (NBE) PL peak, the biaxial compressive stress in the intrinsic layer was found to be 0.4GPa. The residual stress was found to be fully relaxed in the regrown layer. The Si doping concentration in the regrown layer was determined to be 2×1019cm−3 based on the pote...

Analytical threshold voltage model for design and evaluation of tri-gate MOSFETs

A framework for assessing fundamental device properties of tri-gate device is presented. The dynamics of the threshold voltage calculation is evaluated for the tri-gate architecture of device. Limited comparison to double gate device is also presented.

Structure and Process Parameter Optimization for Sub-10nm Gate Length Fully Depleted N-Type SOI MOSFETs by TCAD Modeling and Simulation

According to most recent 2004 International Technology Roadmap for Semiconductor (2004 ITRS), the high performance (HP) MOSFET physical gate length will be scaled to 9nm (22nm technology node) in 2016. We investigate the manufacturability of this sub-10nm gate length fully depleted SOI MOSFET by TCAD simulation. The commercial device simulator ISE TCAD is used. While it is impractical for experiments currently, this study can be used to project performance goals for aggressively scaled devices. In this paper, we will optimize different structure and process parameters at this gate length, such as body thickness, oxide thickness, spacer width, source/drain doping concentration, source/drain doping abruptness, channel doping concentration etc. The sensitivity of device electrical parameters, such as Ion, Ioff, DIBL, Sub-threshold Swing, threshold voltage, trans-conductance etc, to physical variations will be considered. The main objective of this study is to identify the key design issues for sub-10nm gate length Silicon based fully depleted MOSFET at the end of the ITRS. The paper will present the final optimized device structure and optimized performance will be reported.

Modeling and Simulation of Narrowband Gap Semiconductor Indium Antimonide (InSb) Based MOSFET

hole mobility reported is 800 cm 2 V -1 s -1 , this makes fast devices based on InSb possible. In our research we have used two separate mobility models to study the mobility field dependency. The Philips unified mobility model is used to make a channel comparison with silicon MOSFET, assuming in InSb the electron and hole mobility has the similar field dependence as in silicon. The DC simulation result of a NMOS transistor with gate length of 200nm is shown in Fig.3. The drain current of InSb NMOS is almost twice as high as the drain current of Si NMOS showing the high current driving capability of InSb MOSFET. The Canali high-field saturation model is used later to adapt to Hydrodynamic mode of transport equations, the DC simulation result of the same device is shown in Fig.4, which shows even better current driving capability of InSb based NMOS due to the high mobility of InSb. And the negative resistance is shown in Fig4, this shows the appropriate mobility modeling method has accounted for the transfer electron effect which is commonly seen in device based on III-V compound semiconductor materials. The scaling effect of InSb based planar MOSFETs have also been simulated, the drain current versus gate voltage at 1 volt drain bias is shown in Fig. 5. The silicon based devices are also simulated for comparison. Both off state leakage current and turn on current of InSb MOSFETs is much higher than that of silicon devices as shown in Fig.6. The high turn on current is due to high mobility of InSb. High off state leakage current however is because InSb has large intrinsic carrier density (ni =1.9×10 16 cm -3 ) which is six order of magnitude higher than that of silicon. Several techniques have been demonstrated to reduce leakage current of InSb based devices, such as exclusion and extraction [4], electromagnetic carrier depletion [10], low temperature operation etc. From Fig.6, both leakage current of Si and InSb devices increase as the device scales down, but leakage current for InSb NMOS shows a less increasing rate than silicon NMOS as the device scales, which shows the InSb devices might have the similar leakage current as silicon device in sub 50nm regime. A traditional method to reduce off state leakage current of InSb device is device cooling as shown in Fig.7. At 200K the InSb NMOS has more than two orders of magnitude less leakage current. Fig.8 shows the DIBL and transconductance affected by device scaling for both InSb and Si. The InSb devices have larger DIBL for sub 100nm device sizes, and have similar

Simulation Study of Source/Drain Doping Profile for 10nm Gate Length Fully Depleted N-type SOI MOSFET

In this paper, we presents detailed simulation study of the impact of source/drain (S/D) doping profile on device performance for 10nm gate length SOI device. We compared the short channel effects ( SCEs), sub-Vth swing and DIBL, Vth roll-off (for fixed gate work function or fixed Ioff by choosing proper metal gate work function) and Ion-Ioff characteristics for different S/D doping abruptness, S/D dopant concentration and background doping concentration. The results show that the abrupt S/D doping has better Ion (double from 8nm/dec to 2nm/dec) because of less resistance, but SCEs and Vth roll-off could be degraded. The higher S/D doping concentration can achieve h igher Ion in spite of worse SCEs and Vth roll-off. Background doping concentration was chosen to be 10cm to emulate intrinsic silicon for this study .