D.W. Barlage

Nitrogen acceptors in bulk ZnO (0001¯) substrates and homoepitaxial ZnO films

Bulk single crystals of unintentionally doped ZnO having charge carrier concentration, ND−NA values of ∼1017 cm−3 were implanted with N+ ions at dosages of 1015 and 1016 cm−2 at 95 keV to a depth of 150 nm. The resulting p−n structure having acceptor concentrations ranging from 1017 to 1018 cm−3 was compared with nitrogen doped homoepitaxial films with ∼8×1017 cm−3 acceptors. Photoluminescence spectra acquired at 8 K showed an increase in the peak for the neutral donor-bound to acceptor-bound transition at 3.210 eV with increasing annealing temperature, thermal activation of a unique donor to acceptor transition due to nitrogen at 3.067 and 3.057 eV for implanted and epitaxial films, respectively; and an increase in the intensity of the defect-related green band at selected temperatures. Electroluminescence measurements at 300 K revealed an ultraviolet band, direct band-to-band recombination at 3.34 eV, donor-acceptor pair recombinations at 3.19 and 3.0 eV, and recombination in the green region centered a...

Electrical and optical properties of ZnO (0001¯) wafers implanted with argon

The electrical and optical properties of (0001¯)-oriented ZnO wafers, implanted with argon at 230keV and dosage of 1015cm−2 have been determined to establish a baseline by which to compare these properties in similar ZnO materials implanted with other dopants. Capacitance-voltage measurements of unimplanted and implanted wafers, annealed in oxygen at 1atm at 50°C intervals between 250 and 850°C for 30min at each temperature, indicated contributions of charged point defects to the overall conductivity of the latter material. Photoluminescence data acquired at 8K of the same two material sets revealed defect bands in the implanted wafers at 2.4 and 2.25eV related to mobile point defects. The results of both studies indicated crystallographic repair of Ar-implanted ZnO commences at 400°C.

Analytical model of source injection for N-type enhancement mode GaN-based Schottky source/drain MOSFET

GaN MOSFET Source/Drain fabrication techniques have been under extensive research, and Ion Implantation (II) and Selective Area reGrowth (SAG) methods have shown the best performance [1, 2]. As an alternative for S/D of GaN MOSFETs beyond II or SAG, the use of metal for S/D of GaN MOSFETs (or Schottky Barrier GaN MOSFET) has been proposed [3]. While a Schottky metal source/drain presents several potential technological advantages [1], one of the greatest issues of GaN Schottky Barrier MOSFETs is that the on-state current is low compared to other GaN MOSFETs that use II or SAG for source and drain. To overcome this issue, a new device structure with gate-to-source/drain overlap was proposed as shown in Fig. 1(c). Synopsis TCAD simulation was performed on the proposed device, which indicated that the on-state current of gate-to-source overlapped device can be increased by 2 orders of magnitude compared to the one without overlap structure, as shown in Fig. 1(b) [4]. This work is devoted to (1) identification of the mechanism that increases the on-state current, (2) development of an analytical model from the mechanism, and (3) physical demonstration of the simulated device.

Optical spectroscopic analysis of selected area epitaxially regrown n+ gallium nitride

Gallium nitride (GaN) metal-insulator-semiconductor field-effect transistor with regrown by selected area metal organic vapor-phase-epitaxy n+ layer has been analyzed by micro-Raman and microphotoluminescence (micro-PL) spectroscopy. The material properties of the regrown n+ layer and the intrinsic layer in the gate region were extracted by using both spectroscopies. The free-carrier concentration of the regrown GaN layer and the intrinsic layer were determined by line shape analysis of the coupled plasmon-phonon mode to be 4.7×1017 and <3×1016cm−3, respectively. The inefficient substitutions of Ga vacancy (VGa) by Si result in relatively low carrier concentration in the regrown GaN layer. From the shift of E2(2) Raman peak and the near-band-edge (NBE) PL peak, the biaxial compressive stress in the intrinsic layer was found to be 0.4GPa. The residual stress was found to be fully relaxed in the regrown layer. The Si doping concentration in the regrown layer was determined to be 2×1019cm−3 based on the pote...

Characterization and modeling of AlGaN/GaN MOS capacitor with leakage for large signal transistor modeling

Dual mode AlGaN/GaN metal oxide semiconductor (MOS) heterostructure field-effect transistor (HFET) devices were fabricated and characterized. In HFET mode of operation the devices showed an f/sub t//spl middot/L/sub g/ product of 12GHz/spl middot//spl mu/m at Vgs=-2 V. The AlGaN devices showed formation of an accumulation layer under the gate in forward bias and a f/sub t//spl middot/L/sub g/ product of 6GHz/spl middot//spl mu/m was measured at Vgs=5 V. A novel piecewise small signal model for the gate capacitance of MOS HFET devices is presented and procedures to extract the capacitance in presence of gate leakage are outlined. The model accurately fits measured data from 45MHz to 10GHz over the entire bias range of operation of the device.

Prospect for III-Nitride Heterojunction MOSFET Structures and Devices

Heterojunction field effect transistors (HFET) for high-frequency and high-power electronics have been an area of active research in recent years as a key enabling technology for applications ranging from wireless communications to power distribution. III-Nitride semiconductors are a leading candidate for fulfilling the material requirements of these devices based on the combination of large bandgap energy, high thermal conductivity, high electron mobility and saturated electron velocity. While III-Nitride HFETs have demonstrated remarkable advances, serious materials related limitations still exist, primarily related to charge states and trapping effects at the semiconductor surface. Several groups have investigated solutions such as the deposition of dielectric passivation layers and asymmetric field-plate gate geometries for controlling the influence of trap states near the metal/semiconductor FET interface. We have demonstrated a metal-oxide semiconductor FET (MOSFET) with a substantially unpinned interface which is capable of establishing substantial charge accumulation under the gate. These III-Nitride MOSFETs may be designed to operate in either depletion mode or enhancement mode. GaN/InGaN heterojunction MOSFETs exhibit enhancement mode peak transconductance at gate voltages V g >+5V, corresponding to energy greater than the bandgap of the underlying semiconductor which provides strong evidence of an unpinned MOS interface. Additionally III-Nitride MOSFETs eliminate the need for field plate gate structures as the electric field geometry in the gate-drain region changes limiting the tunneling of charge to unfilled surface states. In depletion mode, low-rf dispersion InGaN/GaN MOSFETs exhibit excellent microwave with ft = 8GHz for optically defined gates dimensions. We review the history of compound semiconductor MOSFET development and overlaying these developments with recent advances in the III-Nitride materials and device research. Differences in chemistry of III-Nitrides relative to all other compound semiconductors and the epitaxial deposition of gate-oxides such as Gadolinium Gallium Oxide (GGO), opens the possibility for dramatically improved devices at microwave and mm-wave frequencies as well as power MOSFET rectifiers. Initial III-Nitride MOSFETs results are presented as well as a quaternary thermodynamic framework for the stability of gate-oxide on nitride semiconductors. We also identify key materials related research challenges expected to impact the ongoing development of III-Nitride MOSFETs.

Projections of Schottky Barrier source-drain Gallium Nitride MOSFET based on TCAD simulation and experimental results

This paper details the use of nickel Schottky barriers as the source and drain for a Schottky barrier GaN MOSFET (SB-MOSFET).

Analytical threshold voltage model for design and evaluation of tri-gate MOSFETs

A framework for assessing fundamental device properties of tri-gate device is presented. The dynamics of the threshold voltage calculation is evaluated for the tri-gate architecture of device. Limited comparison to double gate device is also presented.

Low field mobility in AlGaN/InGaN MOS-HFETs from cold-FET measurements

Low field mobility can be experimentally determined using high-frequency S-parameter measurements. The extraction procedure used is based on the capacitance-conductance method commonly used for MOSFETs [1] and is used to estimate the low field mobility in 0.25 μm AlGaN/InGaN MOS-HFETs. Extraction primarily depends on channel conductance and charge sheet density. The former is usually obtained through DC measurement at low drain bias [2]. However, unless the source/drain series resistances are negligible a correction must be made to the resulting conductance. The latter quantity is typically found from low-frequency split C-V measurements at zero drain-source bias, thus requiring a separate measurement [3]. The difference in drain-source bias between the channel conductance and charge sheet density necessitates an experimental change when using the typical measurement approach [4].

Gate leakage effects of annealing Lanthanum Oxide on Gallium Nitride

Gallium Nitride, a wide band gap semiconductor, is a strong candidate for next generation power electronic devices due to its high thermal conductivity and critical electric field. It is desirable to increase the switching speed and operating voltage of power transistors and diodes to decrease loss and increase efficiency. Junction temperatures and switching speeds desired for high power field-effect transistors are approaching the limit of silicon-based devices, therefore new alternatives must be examined [1, 2, 3]. Toyota has specifically stated that wide band gap semiconductor devices offer distinct and desirable advantages over silicon due to high electric field breakdown and thermal capacity [4]. A key performance benchmark of FETs is channel sheet charge, ns. Figure 1 details several reported values of sheet charge for recent GaN-based devices as compared to high-k on Silicon. Previous results for Lanthanum Oxide on Gallium Nitride yielded record breaking sheet charge, however several process integration challenges still exist.