Doug Barlage

Transmission electron microscopy studies of regrown GaN Ohmic contacts on patterned substrates for metal oxide semiconductor field effect transistor applications

Contact selected area regrowth of GaN was performed by metal organic chemical vapor deposition using a silicon nitride dielectric hard mask to define plasma etched recesses and to define source-drain regions. A low temperature regrowth process at 750–850°C was adopted to limit lateral overgrowth. High resolution electron microscopy images and selected area diffraction confirmed the regrowth selectivity and revealed that the low temperature regrown GaN is epitaxial and has a wurtzite crystal structure. I-V characteristics of the fabricated metal oxidesemiconductor field effect transistor show enhancement mode operation.

Pulsed-IV and RF waveform measurements of unique high-K dielectric GaN MOSFETs

This paper demonstrates the capabilities of a state of the art RF waveform measurement system to explore the RF performance of new compound semiconductor MOSFET devices. Pulsed IV and time domain waveform measurements are presented for recently developed GaN MOSFET devices with high-K epitaxially grown gate dielectrics. The results demonstrate promising performance for first generation devices, with RF power densities above 1 W/mm. The waveform measurements point the way forward for improving future devices by giving direct visual feedback on where performance is being lost.

Structure and Process Parameter Optimization for Sub-10nm Gate Length Fully Depleted N-Type SOI MOSFETs by TCAD Modeling and Simulation

According to most recent 2004 International Technology Roadmap for Semiconductor (2004 ITRS), the high performance (HP) MOSFET physical gate length will be scaled to 9nm (22nm technology node) in 2016. We investigate the manufacturability of this sub-10nm gate length fully depleted SOI MOSFET by TCAD simulation. The commercial device simulator ISE TCAD is used. While it is impractical for experiments currently, this study can be used to project performance goals for aggressively scaled devices. In this paper, we will optimize different structure and process parameters at this gate length, such as body thickness, oxide thickness, spacer width, source/drain doping concentration, source/drain doping abruptness, channel doping concentration etc. The sensitivity of device electrical parameters, such as Ion, Ioff, DIBL, Sub-threshold Swing, threshold voltage, trans-conductance etc, to physical variations will be considered. The main objective of this study is to identify the key design issues for sub-10nm gate length Silicon based fully depleted MOSFET at the end of the ITRS. The paper will present the final optimized device structure and optimized performance will be reported.

Simulation Study of Source/Drain Doping Profile for 10nm Gate Length Fully Depleted N-type SOI MOSFET

In this paper, we presents detailed simulation study of the impact of source/drain (S/D) doping profile on device performance for 10nm gate length SOI device. We compared the short channel effects ( SCEs), sub-Vth swing and DIBL, Vth roll-off (for fixed gate work function or fixed Ioff by choosing proper metal gate work function) and Ion-Ioff characteristics for different S/D doping abruptness, S/D dopant concentration and background doping concentration. The results show that the abrupt S/D doping has better Ion (double from 8nm/dec to 2nm/dec) because of less resistance, but SCEs and Vth roll-off could be degraded. The higher S/D doping concentration can achieve h igher Ion in spite of worse SCEs and Vth roll-off. Background doping concentration was chosen to be 10cm to emulate intrinsic silicon for this study .