Chanha Park

CD uniformity improvement by active scanner corrections

As resolution shrinks, also the demands for litho CD Uniformity are becoming tighter. In replicating the mask pattern into photoresist, a sequence of modules within the patterning cluster (coat, expose, develop, etch) is responsible for CD non-uniformity. So far, the strategy has been to make the contribution of each of these modules as small as possible. The CD Uniformity can be improved in a more efficient way by compensating the various error sources with adapted dose profiles on the scanner. An inventory is made of the requirements for this compensation mechanism. In more detail a description is given how the scanner can apply these dose corrections. With experiments, the feasibility of the concept is proven. Improvements in CD Uniformity over 5nm are demonstrated, both on test structures as well as on real device layers.

Application of DBM system to overlay verification and wiggling quantification for advanced process

With the shrinkage of semiconductor device scales, advanced semiconductor industries face tremendous challenges in process control. As lithography and etch processes are pushed to get smaller dimensions, the overlay and wiggling control are hot issues due to the limiting of pattern performance. Many chip makers are using Double Patterning Technology (DPT) process to overcome design rule limitations but they are also concerned about overlay control. In DPT process, obtaining accurate overlay data by measuring overlay marks with traditional metrology is difficult because of the difference of shape and position between cell pattern and overlay marks. Cell to overlay mark miss-match will occur when there is lens aberration or mask registration error. Therefore, the best way to obtain accurate overlay data without error is to measure the real cell itself. The overlay of the cell array using DPT process can be measured by analyzing the relative position of the 2nd exposed pattern to the 1st exposed pattern. But it is not easy to clearly distinguish a 1st layer and 2nd layer in a patterned cell array image using CD SEM. The Design Based Metrology (DBM)-system can help identify which cell pattern is a 1st or 2nd layer, so overlay error between the 1st and 2nd layers at DPT process can be checked clearly. Another noticeable problem in advanced processing is wiggling. The wiggling of a pattern become severe by the etch process and must be controlled to meet electrical characteristics of what the semiconductor device requires. The 1st stage of wiggling control is to understand the level of wiggling which is crucial to device performance. The DBM-system also can be used for quantification of wiggling by determining specially designed parameters. In this paper we introduce overlay verification and wiggling quantification through new methodology for advanced memory devices.

High NA polarized light lithography for 0.29k1 process

Polarization is becoming very important technology in micro-lithography at the higher NA lithography for much smaller design. The wide and intensive studies to apply the polarization technology into lithography application have been achieved. Source polarization, mask polarization and projection lens polarization could make different printing results compared to non-polarization cases. Especially k1 factor below 0.3 needs aggressive resolution enhancement techniques. Environmental parameters such as mask CD, lens aberration, stray light, image plane deviation and resist characteristic make CD controllability worse in the very low k1 regime. The polarization technology can contribute to getting better imaging performance. This experiment is challenging k1 factor down to 0.29 with the source polarization function. The source polarization effect on real device will be shown through the simulation and actual printing process using 6% attenuated PSM. The related OPC strategy with the polarized source will also be discussed.

The improvement of DOF for sub-100nm process by focus scan

As the design rule of device shrinks down, it is difficult to enlarge the process window, especially DOF (Depth of Focus). It has shown good results in resolution issues with short wavelength, high NA aperture and several RET (Resolution Enhancement Technique) like special illuminator and mask techniques and so on. But it needs to be challenged for DOF process window in contact / via process having various pitch and pattern location. It is a key point in sub 100nm process development and product. It is demonstrated that focus scan method is effective for DOF improvement in contact and via layers. Focus Scan method is one of the focus drilling techniques; it is realized to tilt wafer stage so that the same point on the wafer field can be exposed in limited continual focus range using multiple focal planes through the slit of scanner tool. In this study, confirmation was inspected for simulation and wafer evaluation for focus scan effects in view of process feasibility. DOF increased over 50% with focus scan in contact mask process even though there are several issues to be solved and considered. Energy Latitude (EL) decreased a little by image contrast drop, but if we consider the process window for evolution of device, it is relatively enough for process. OPC or Bias tuning is needed for application in contact layer having various pitch and location, and overlay issues are needed to confirm for each illuminator. From these experiments, it is found that DOF margin can easily be enhanced using focus scan method. Also some fine tuning is required to adequately use this method on production devices.

Analysis of the impact of pupil shape variation by pupil fit modeling

As K1 factor for mass-production of memory devices has been decreased to almost its theoretical limit, the process window of lithography is getting much smaller and the production yield has become more sensitive to even small variations of the process in lithography. So it is necessary to control the process variations more tightly than ever. In mass-production, it is very hard to extend the production capacity if the tool-to-tool variation of scanners and/or scanner stability through time is not minimized. One of the most critical sources of variation is the illumination pupil. So it is critical to qualify the shape of pupils in scanners to control tool-to-tool variations. Traditionally, the pupil shape has been analyzed by using classical pupil parameters to define pupil shape, but these basic parameters, sometimes, cannot distinguish the tool-to-tool variations. It has been found that the pupil shape can be changed by illumination misalignment or damages in optics and theses changes can have a great effect on critical dimension (CD), pattern profile or OPC accuracy. These imaging effects are not captured by the basic pupil parameters. The correlation between CD and pupil parameters will become even more difficult with the introduction of more complex (freeform) illumination pupils. In this paper, illumination pupils were analyzed using a more sophisticated parametric pupil description (Pupil Fit Model, PFM). And the impact of pupil shape variations on CD for critical features is investigated. The tool-to-tool mismatching in gate layer of 4X memory device was demonstrated for an example. Also, we interpreted which parameter is most sensitive to CD for different applications. It was found that the more sophisticated parametric pupil description is much better compared to the traditional way of pupil control. However, our examples also show that the tool-to-tool pupil variation and pupil variation through time of a scanner can not be adequately monitored by pupil parameters only, The best pupil control strategy is a combination of pupil parameters and simulated CD using measured illumination pupils or modeled pupils.

Aberration sensitivity control for the isolation layer in low-k1 DRAM process

One of the crucial factors to take mostly into account the development and production of 130 nm node in low k1 DRAM process is the lens aberration sensitivity control of optical lithographic tools. To meet the required specification these impact of lens aberration resulting from reducing process window caused by pattern deformation, CD uniformity, CD asymmetry, and pattern shift etc. should be understood and considered. In this study, we mainly focused on the aberration sensitivity control for the DRAM isolation layer that is very sensitive to odd components such as coma and three-foil etc. There are a few methods to do this, but the application of extreme sigma setting that is the powerful manner to improvement of asymmetric pattern and layout rotation were examined. It was confirmed that the simulated image and real patterning results for left-right CD difference came from aberrated lens are well matched. In addition, why is the extreme sigma setting more effective than standard settings was investigated with analysis of diffraction patterns on pupil filling of projection lens optics combined with Zernike coefficients phase map.

Application of DBM tool for detection of EUV mask defect

Extreme ultraviolet lithography (EUVL) is one of the most leading lithography technologies for high volume manufacturing. The EUVL is based on reflective optic system therefore critical patterning issues are arisen from the surface of photomask. Defects below and inside of the multilayer or absorber of EUV photomask is one of the most critical issues to implement EUV lithography in mass production. It is very important to pick out and repair printable mask defects. Unfortunately, however, infrastructure for securing the defect free photomask such as inspection tool is still under development furthermore it does not seem to be ready soon. In order to overcome the lack of infrastructures for EUV mask inspection, we will discuss an alternative methodology which is based on wafer inspection results using DBM (Design Based Metrology) tool. It is very challenging for metrology to quantify real mask defect from wafer inspection result since various sources are possible contributor. One of them is random defect comes from poor CD uniformity. It is probable that those random defects are majority of a defect list including real mask defects. It is obvious that CD uniformity should be considered to pick out only a real mask defect. In this paper, the methodology to determine real mask defect from the wafer inspection results will be discussed. Experiments are carried out on contact layer and on metal layer using mask defect inspection tool, Teron(KLA6xx) and DBM (Design Based Metrology) tool, NGR2170™.

Resolution enhancement techniques for contact hole printing of sub-50nm memory device

In resolution limited lithography process, the contact hole pattern is one of the most challenging features to be printed on wafer. A lot of lithographers struggle to make robust hole patterns under 45nm node, especially if the contact hole patterns are composed of dense array and isolated hole simultaneously. The strong OAI(Off Axis Illumination) such as dipole is very useful technique to enhance resolution for specific features. However the contact hole formed by dipole illumination usually has elliptical shape and the asymmetric feature leads to increment of chip size. In this paper, we will explore the lithographic feasibility for the coexisting dense array with isolated contact holes and the technical issues are investigated to generate finer contact hole for both dense and isolated feature. Conventional illumination with resist shrinkage technique will be used to generate dense array and isolated contact hole maintaining original shape for the sub-50nm node memory device.

CD control at low K1 optical lithography in DRAM device

In this work, CD control issue at 0.37 K1 optical lithography will be discussed in terms of lens aberration sensitivity. Specific aberration terms that affect CD asymmetry on isolation, word line and storage node layers were investigated by simulation and CD uniformity measurement. The lens aberration was characterized by LITEL ISI (In-Situ Interferometer) and the aberration sensitivity was investigated by Solid-C aerial image simulation. From this result, we can understand the relation between some significant Zernike terms and CD control of DRAM’s critical layers.

Model based cell-array OPC development for productivity improvement in memory device fabrication

Traditionally, optical proximity correction (OPC) on cell array patterns in memory layout uses simple bias rules to correct hierarchically-placed features, but requires intensive, rigorous lithographic simulations to maximize the wafer process latitude. This process requires time-consuming procedures to be performed on the full chip (excluding the cell arrays) to handle unique cell features and layout placements before (and even sometimes after) OPC. The time required limits productivity for both mask tapeouts and the wafer process development. In this paper, a new cell array OPC flow is introduced that reduces turnaround-time for mask tapeouts from days to hours, while maintaining acceptable OPC quality and the perfect geometric consistency on the OPC output that is critical for memory manufacturing. The flow comprises an effective sub-resolution assist features (SRAFs) insertion and OPC for both the cell array and the peripheral pattern areas. Both simulation and experimental results from actual wafer verification are discussed.