Donggyu Yim

CD uniformity improvement by active scanner corrections

As resolution shrinks, also the demands for litho CD Uniformity are becoming tighter. In replicating the mask pattern into photoresist, a sequence of modules within the patterning cluster (coat, expose, develop, etch) is responsible for CD non-uniformity. So far, the strategy has been to make the contribution of each of these modules as small as possible. The CD Uniformity can be improved in a more efficient way by compensating the various error sources with adapted dose profiles on the scanner. An inventory is made of the requirements for this compensation mechanism. In more detail a description is given how the scanner can apply these dose corrections. With experiments, the feasibility of the concept is proven. Improvements in CD Uniformity over 5nm are demonstrated, both on test structures as well as on real device layers.

New OPC verification method using die-to-database inspection

The minimum feature size of new generation memory devices is approaching down to 50 nm era. And a very precise CD control is demanded not only for cell layouts but also for core and peripheral layouts of DRAM devices. However, as NA of lens system grows higher and higher and Resolution Enhancement Techniques (RETs) becomes more and more aggressive, isolated-dense bias increases and process window for the core and peripheral layouts decreases dramatically. So, the burden of OPC increases in proportion and it is requisite to verify as many features as possible on wafer. If possible, it would be desirable to verify all the features in a die. Recently, a novel inspection tool has been developed which can verify all kinds of patterns on wafer based on Die to Database copmarison method. It can identify all the serious systematic defects of nm order size error from the original layout target and feed back the systematic error points to OPC for more accurate model tuning. In addition we can obtain the full field CD distribution diagram of some specific transistors with hundreds of thousands of measurement data. So, we can analyze the root cause of the CD distribution in a field, such as mask CDU or lens aberrations and so on. And we can also perform Process Window Qualification of all the features in a die. In this paper, OPC verification methodology using the new inspection tool will be introduced and the application to the analysis of full field CD distribution and Process Window Qualification will be presented in detail.

Evaluation of shadowing and flare effect for EUV tool

One of the major issues introduced by development of Extreme Ultra Violet Lithography (EUV) is high level of flare and shadowing introduced by the system. Effect of the high level flare degrades the aerial images and may introduce unbalanced Critical Dimension Uniformity (CDU) and so on. Also due to formation of the EUV tool, shadowing of the pattern is another concern added from EUVL. Shadowing of the pattern will cause CD variation for pattern directionality and position of the pattern along the slit. Therefore, in order to acquire high resolution wafer result, correction of the shadowing and flare effect is inevitable for EUV lithography. In this study, we will analyze the effect of shadowing and flare effect of EUV alpha demo tool at IMEC. Simulation and wafer testing will be analyzed to characterize the effect of shadowing on angle and slit position of the pattern. Also, flare of EUV tool will be plotted using Kirks disappearing pad method and flare to pattern density will also be analyzed. Additionally, initial investigation into actual sub 30nm Technology DRAM critical layer will be performed. Finally simulation to wafer result will be analyzed for both shadowing and flare effect of EUV tool.

Advanced process control with design-based metrology

K1 factor for development and mass-production of memory devices has been decreased down to below 0.30 in recent years. Process technology has responded with extreme resolution enhancement technologies (RET) and much more complex OPC technologies than before. ArF immersion lithography is expected to remain the major patterning technology through under 35 nm node, where the degree of process difficulties and the sensitivity to process variations grow even higher. So, Design for manufacturing (DFM) is proposed to lower the degree of process difficulties and advanced process control (APC) is required to reduce the process variations. However, both DFM and APC need much feed-back from the wafer side such as hot spot inspection results and total CDU measurements at the lot, wafer, field and die level. In this work, we discuss a new design based metrology which can compare SEM image with CAD data and measure the whole CD deviations from the original layouts in a full die. It can provide the full information of hot spots and the whole CD distribution diagram of various transistors in peripheral regions as well as cell layout. So, it is possible to analyze the root cause of the CD distribution of some specific transistors or cell layout, such as OPC error, mask CDU, lens aberrations or etch process variation and so on. The applications of this new inspection tool will be introduced and APC using the analysis result will be presented in detail.

Comprehensive EUV lithography model

As EUV lithography nears pilot-line stage, photolithography modeling becomes increasingly important in order for engineers to build viable, production-worthy processes. In this paper, we present a comprehensive, calibrated lithography model that includes optical effects such as mask shadowing and flare, combined with a stochastic resist model that can predict effects such as line-edge roughness. The model was calibrated to CD versus pitch data with varying levels of flare, as well as dense lines with varying degrees of mask shadowing. We then use this model to investigate several issues critical to EUV. First, we investigate EUV photoresist technology: the impact of photoelectron-PAG exposure kinetics on photospeed, and then we examine the trade-off between LWR and photospeed by changing quencher loading in the photoresist model. Second, we compare the predicted process windows for dense lines as flare and lens aberrations are reduced from the levels in the current alpha tools to the levels expected in the beta tools. The observed interactions between optical improvements and resist LWR indicate that a comprehensive model is required to provide a realistic evaluation of a lithography process.

Wide applications of design based metrology with tool integration

Recently several DBMs(Design Based Metrologies) are introduced for the wafer verification and feed back to DFM. The major applications of DBM are OPC accuracy feed back, process window qualification and advanced process control feed back. In general, however, DBM brings out huge amount of measurement data and it is necessary to provide special server system for uploading and handling the raw data. And since it also takes much time and labor to analyze the raw data for valuable feed back, it is desirable to connect to EDA tools such as OPC tools or MBV(Model Based Verification) tools for data analysis. If they can communicate with a common language between them, the DBM measurement result can be sent back to OPC or MBV tools for better model calibration. For advanced process control of wafer CDU, DBM measurement results of field CDU can be fed back to scanner for illumination uniformity correction. In this work, we discuss tool integration of DBM with other tools like EDA tools. These tool integrations are targeted for the verification procedure automation and as a result for faster and more exact analysis of measurement data. The procedures of tool integration and automatic data conversion between them will be presented in detail.

Evaluation of Inverse Lithography Technology for 55nm-node memory device

Model based OPC has been generally used to correct proximity effects down to ~50 nm critical dimensions at k1 values around 0.3. As design rules shrink and k1 drops below 0.3, however; it is very hard to obtain enough process window and acceptable MEEF (Mask Error Enhancement Factor) with conventional model based OPC. Recently, ILT (Inverse Lithography Technology) has been introduced and has demonstrated wider process windows than conventional OPC. The ILT developed by Luminescent uses level-set methods to find the optimal photo mask layout, which maximizes the process window subject to mask manufacturing constraints. We have evaluated performance of ILT for critical dimensions of 55nm, printed under conditions corresponding to k1 ~ 0.28. Results indicated a larger process window and better pattern fidelity than obtained with other methods. In this paper, we present the optimization procedures, model calibration and evaluation results for 55 nm metal and contact layers and discuss the possibilities and the limitations of this new technology.

Application of DBM system to overlay verification and wiggling quantification for advanced process

With the shrinkage of semiconductor device scales, advanced semiconductor industries face tremendous challenges in process control. As lithography and etch processes are pushed to get smaller dimensions, the overlay and wiggling control are hot issues due to the limiting of pattern performance. Many chip makers are using Double Patterning Technology (DPT) process to overcome design rule limitations but they are also concerned about overlay control. In DPT process, obtaining accurate overlay data by measuring overlay marks with traditional metrology is difficult because of the difference of shape and position between cell pattern and overlay marks. Cell to overlay mark miss-match will occur when there is lens aberration or mask registration error. Therefore, the best way to obtain accurate overlay data without error is to measure the real cell itself. The overlay of the cell array using DPT process can be measured by analyzing the relative position of the 2nd exposed pattern to the 1st exposed pattern. But it is not easy to clearly distinguish a 1st layer and 2nd layer in a patterned cell array image using CD SEM. The Design Based Metrology (DBM)-system can help identify which cell pattern is a 1st or 2nd layer, so overlay error between the 1st and 2nd layers at DPT process can be checked clearly. Another noticeable problem in advanced processing is wiggling. The wiggling of a pattern become severe by the etch process and must be controlled to meet electrical characteristics of what the semiconductor device requires. The 1st stage of wiggling control is to understand the level of wiggling which is crucial to device performance. The DBM-system also can be used for quantification of wiggling by determining specially designed parameters. In this paper we introduce overlay verification and wiggling quantification through new methodology for advanced memory devices.

OPC verification and hotspot management for yield enhancement through layout analysis

As the design rule shrinks down, various techniques such as RET, DFM have been continuously developed and applied to lithography field. And we have struggled not only to obtain sufficient process window with those techniques but also to feedback hot spots to OPC process for yield improvement in mass production. OPC verification procedure which iterates its processes from OPC to wafer verification until the CD targets are met and hot spots are cleared is becoming more important to ensure robust and accurate patterning and tight hot spot management. Generally, wafer verification results which demonstrate how well OPC corrections are made need to be fed back to OPC engineer in effective and accurate way. First of all, however, it is not possible to cover all transistors in full-chip with some OPC monitoring points which have been used for wafer verification. Secondly, the hot spots which are extracted by OPC simulator are not always reliable enough to represent defective information for full-chip. Finally, it takes much TAT and labor to do this with CD SEM measurement. These difficulties on wafer verification would be improved by design based analysis. The optimal OPC monitoring points are created by classifying all transistors in full chip layout and Hotspot set is selected by pattern matching process using the NanoScopeTM, which is known as a fast design based analysis tool, with a very small amount of hotspots extracted by OPC simulator in full chip layout. Then, each set is used for wafer verification using design based inspection tool, NGR2150TM. In this paper, new verification methodology based on design based analysis will be introduced as an alternative method for effective control of OPC accuracy and hot spot management.

Feasibility of EUVL thin absorber mask for minimization of mask shadowing effect

Conventional EVUL mask has 80nm absorber height which brings considerable shadowing effect. H-V CD bias of 40nm line and space by shadowing effect is more than 4nm, and that is expected to increase much more for narrower patterns by simulation. However various reports have been presented on mask shadowing bias correction, experimental results are not reliable to derive required mask bias correctly. Even more difficulty will arise when complex 2D structures are taken into account. Therefore minimization of shadowing effect by reducing absorber thickness is desirable. To transfer EUV lithography from experimental stage to HVM era, we need to find optimum absorber height of EUVL mask which allows us less shadowing effect with minimum loss of process window. In this paper, we present optimal absorber height of EUV mask which has been found in terms of shadowing effect and process window by simulation and exposure. To find minimized absorber height experimentally, we will compare the printing result of conventional and thin mask stack using simple 1:1 line and space and island patterns. Simulated H-V CD bias and process window will be presented.