Chao-g Chen

Channel Stress Modulation and Pattern Loading Effect Minimization of Milli-Second Super Anneal for Sub-65nm High Performance SiGe CMOS

In this paper, we present an advanced integration approach using milli-second anneal technique to enhance device performance. In addition to enhanced poly-silicon activation, the device gain resulted from channel stress modulation, and retarded dopant diffusion can be obtained through process optimization including rapid-thermal anneal (RTA), capping layer, and milli-second anneal. More than 15% NMOS performance gain is demonstrated without undergoing milli-second-anneal-induced pattern loading effect and re-crystallization defect. No obvious stress relaxation and driving current degradation are observed in epi-SiGe PMOS. Moreover, the performance gain is increased while lowering the RTA temperature, suggesting that our proposed approach may open an alternative pathway for 45nm technology node and beyond

In 0.53 Ga 0.47 As MOSFETs with high channel mobility and gate stack quality fabricated on 300 mm Si substrate

In_0.53Ga_0.47As channel MOSFETs were fabricated on 300 mm Si substrate. The epitaxial In_0.53Ga_0.47As channel layer exhibits high Hall electron mobility comparable to those grown on lattice matched InP substrates. Excellent device characteristics (SS~95 mV/dec., I_on/I_off ~10⁵, DIBL ~51 mV/V at V_ds = 0.5V for L_g=150 nm device) with good uniformity across the wafer were demonstrated. The extracted high field effect mobility (μ_EF = 1837 cm²/V-s with EOT ~ 0.9 nm) is among the highest values reported for surface channel In_0.53Ga_0.47As MOSFETs.

Modeling and Characterization of Advanced Phosphorus Ultra Shallow Junction Using Germanium and Carbon Coimplants

A continuum model of phosphorus diffusion with germanium and carbon coimplant has been proposed and calibrated based on secondary ion mass spectroscopy (SIMS) profiles aiming at ultra shallow junction (USJ) formation in advanced CMOS technologies. The phosphorus diffusion behaviors are well captured by our model under various implant and annealing conditions, representing a significant step towards advanced n-type USJ formation technique using phosphorus and carbon coimplant for aggressively scaled CMOS technologies.