Chao-Chi Hong

Degradation in metal-oxide-semiconductor structure with ultrathin gate oxide due to external compressive stress

The effect of external stress on metal-oxide-semiconductor (MOS) structure with ultrathin gate oxide (∼1.5 nm) was studied. J–V characteristics of fresh and stressed samples revealed that the tensile stress had little effect on J–V curves, whereas the compressive stress obviously increased the leakage current by about several hundred in percentages with respect to the fresh sample, in both positive and negative gate biases. This increase in leakage current was suggested to be attributed to the increase of interface states and silicon bulk traps under external compressive stress in the MOS device with an inherent tensile stressed silicon. In addition, we also found that once the device was damaged by the previously applied compressive stress, the second applied compressive stress of the same magnitude would not create more damage unless the device was breakdown.

Silicon Metal-Oxide-Semiconductor Solar Cells with Oxide Prepared by Room Temperature Anodization in Hydrofluosilicic Acid Solution

It had heen reported that liquid-phase deposition (LPD) using saturated hydrofluosilicic acid (H 2 SiF 6 ) is useful for silicon metal-oxide-semiconductor (MOS) solar cells However, the LPD preparation time is long. In this work, anodic oxidation in saturated H 2 SiF 6 solution is proposed as an alternative method to grow the room temperature oxides for MOS solar cells It was found that the oxide preparation time is reduced significantly without sacrificing the efficiency in comparison with that by the LPD method. The oxide prepared by anodization (ANO) in H 2 SiF 6 was found to be deposition-like which is different from that by ANO in H 2 O. The oxidation time is about 5 min for the ANO method, but it is up to 4 h for the LPD method to obtain about 50 A thick oxide. After adding intercathode semitransparent thin A1 film between thick A1 cathode lines, it is apparent that all performances of the solar cells are improved. The reliability and efficiency of solar cells can also be improved above the 200°C, 5 min postmetalization annealing treatment, and a conversion efficiency of 9.5% is shown.

Enhanced thermally induced stress effect on an ultrathin gate oxide

The effects of thermal stress on the electrical characteristics of metal–oxide–semiconductor diodes with oxides in an ultrathin regime were studied. By centering a quartz ring as a heat sink beneath the silicon wafer, the introduced temperature gradient results in a corresponding hat-like shape thickness distribution for an oxide grown on the wafer with a rapid thermal processing system. The enhanced exterior tensile and compressive thermal stresses due to introduced temperature gradient make the oxides exhibit less and more substrate injection saturation current Jsat, respectively, in comparison to control oxides. Their flatband voltage VFB data also clearly show the dependency of effective charge number density Neff on exterior thermal stress. A stress distribution model is proposed to explain the observation. Co-60 irradiation was also performed on the stressed samples to observe this stress extent by examining the variation of electrical characteristics. It was found that an oxide grown on a wafer in ...

Thickness-dependent stress effect in p-type metal-oxide-semiconductor structure investigated by substrate injection current

The effects of oxide, Si wafer, and gate Al thicknesses on the substrate injection currents (Jsub) of p-type metal–oxide–semiconductor structures with ultrathin oxides are studied. Jsub is reported to be both trap-related (interface and Si bulk) and Si band gap-related (intrinsic carrier concentration). Both mechanisms have given rise to the stress near the Si/SiO2 interface. Current–voltage and capacitance–voltage characterizations reveal that Jsub increases with oxide thickness, which is suggested to be dominated by the trap-related mechanism. A stronger dependence of Jsub on a change in oxide thickness is observed for a thicker Si wafer, which is proposed to be mainly caused by the band gap-related mechanism. Furthermore, a thicker gate Al introduces a higher Jsub, which is proposed to be due to both the trap-related and the band gap-related mechanisms.

Reduction in leakage current of low-temperature thin-gate oxide by repeated spike oxidation technique

A novel repeated spike oxidation (RSO) technique had been used to grow low-temperature thin-gate oxide. Around the similar effective oxide thickness extracted from the capacitance-voltage (C-V) curves under quantum mechanical effect consideration, the leakage currents of RSO samples were near one order of magnitude lower than those of typical ones. Flat band voltage shift or electron trapping in RSO oxides during current-voltage (I-V) measurement had not been observed. The reduction of interface state densities and the improvement in oxide uniformity would be the possible reasons for the reduction in leakage currents of RSO samples.

Improvement in oxide thickness uniformity by repeated spike oxidation

A new repeated spike oxidation (RSO) method used in a rapid thermal processing system was proposed in this work. Simulation results predict the temperature distribution on the wafer would be improved by this RSO method. We proposed that the improvement in wafer temperature uniformity is mainly caused by self-compensation in radiation heat absorption rate. Experimental data pointed out that the new method can produce more uniform oxide thickness than the conventional one under an intentionally created nonuniform heating environment.

Improvement in ultrathin rapid thermal oxide uniformity by the control of gas flow

A methodology to improve the temperature uniformity for the wafer in a rapid thermal processing (RTP) system is presented. The work aims at the temperature compensation at the wafer surface by thermal convection. From simulation results of the flow field, it is seen that the cold gas, while flowing from the periphery of the wafer toward the wafer center, causes a lower pressure at and around the center. This lower pressure is due to the flow away of gas by buoyancy and it aggregates thermal nonuniformity. A technique is suggested that consists of suppressing the upward gas flow using a transparent quartz cap above the monitored wafer. Simulation and experimental results show that by implementing this technique, the temperature uniformity of the wafer is improved.

Stress distribution on [100] Si wafer mapped by novel I-V analysis of MOS tunneling diodes

The current-voltage (I-V) characteristics of metal-oxide-semiconductor tunneling diodes distributed over a 3-in Si wafer were analyzed to investigate the stress distribution on the wafer. Generally, the substrate injection saturation current (J/sub sat/) decreases as the gate injection leakage current (J/sub g/) increases, the latter being dominated by oxide thickness via a trap related mechanism. A universal curve to fit all analyzed data was found and it is suggested that devices with extremely high (low) J/sub sat/ at a given J/sub g/ should be located in areas of the silicon lattice with relatively high external compressive (tensile) stress because of the stress-induced bandgap variation effect. The mapped locations of the highly stressed devices on a 3-in [100] Si wafer correspond to the patterns of slips caused by thermal stress during rapid thermal processing, as described in previous reports.

Carrier dynamics of terahertz emission based on strained SiGe/Si single quantum well

We report analysis of the carrier distribution during terahertz emission process with carrier–phonon interaction based on p-doped strained SiGe/Si single quantum-well. The results of this analysis show that a considerable number of carriers can penetrate the phonon wall to become “hot” carriers on an approximately picosecond timescale. These hot carriers relax after the removal of the applied voltage, generating a “second” emission in the measurement. This investigation provides an understanding of the carrier dynamics of terahertz emission and has an implication for the design of semiconductor terahertz emitters.

Thermal stress at wafer contact points in rapid thermal processing investigated by repeated spike treatment before oxidation

Repeated spike treatment (RST), which was characterized by setting the temperature to ramp up and down repeatedly, was employed to study the stress effect on wafers by annealing the silicon wafers in ambient N2, followed by oxidation in O2. These RST+O samples had three apparent local thick oxide regions that adjoined the contacts of the three-pin quartz holder, as opposed to the typical+O samples annealed with a conventional temperature profile before the same oxidation process. It was observed that defects could be created on the silicon surface due to the high thermal stress at contacts during RST, and that the oxidation rate of these damaged zones was greatly increased. I–V data show that for a similar oxide thickness, the leakage currents in RST+O samples are higher and more scattered than those in typical+O samples. C–V measurements illustrate that RST+O samples have higher interface state densities than typical+O samples. These enhanced degradation phenomena could be caused by the RST, which result...