-Yun Chang

5nm-gate nanowire FinFET

A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage cur-rent less than 10 nA/ /spl mu/m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

25 nm CMOS Omega FETs

Low leakage and low active-power 25 nm gate length C-MOSFETs are demonstrated for the first time with a newly proposed Omega-(/spl Omega/) shaped structure, at a conservative 17-19 /spl Aring/ gate oxide thickness, and with excellent hot carrier immunity. For 1 volt operation, the transistors give drive currents of 1440 /spl mu/A//spl mu/m and 780 /spl mu/A//spl mu/m with off state leakage currents of 8 nA//spl mu/m and 0.4 nA//spl mu/m for N-FET and P-FET, respectively. A low voltage version achieves, at 0.7 V, drive currents of 1300 /spl mu/A//spl mu/m for N-FET and 550 /spl mu/A//spl mu/m for P-FET at an off current of 1 /spl mu/A//spl mu/m. N-FET gate delay (CV/I) of 0.39 ps and P-FET gate delay of 0.88 ps exceed International Technology Roadmap for Semiconductors (ITRS) projections.

A 25-nm gate-length FinFET transistor module for 32nm node

FinFET is the most promising double-gate transistor architecture [1] to extend scaling over planar device. We present a high-performance and low-power FinFET module at 25 nm gate length. When normalized to the actual fin perimeter, N-FinFET and P-FinFET have 1200 and 915 µA/µm drive current respectively at 100nA/µm leakage under 1V. To our knowledge this is the best FinFET drive current at such scaled gate length. This scaled gate length enables this FinFET transistor for 32nm node insertion. With aggressive fin pitch scaling, the effective transistor width is approximately 1.9X and 2.7X over planar for typical logic and SRAM on the same layout area (i.e., silicon real estate). Due to superior electrostatics and reduced random dopant fluctuation, this high drive current can be readily traded with VDD scaling for low power.

20nm gate bulk-finFET SONOS flash

High-performance FinFET SONOS (silicon-oxide-nitride-oxide-silicon) flash cells with gate length down to 20nm have been fabricated and operated successfully on bulk-silicon substrate for the first time. A program/erase window of 2V has been achieved with high P/E speed (TP equiv 10mus and TE equiv 1ms), and a 1.5V window remained after 10 years at room temperature. Multi-level storage is also obtained with DeltaVt > 4V and TP,E equiv 1 ms. Operation voltages are not more than 7V in the two applications. Gate disturb issues are alleviated by applying an appropriate bias on unselected bit lines

A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

We show that FinFET, a leading transistor architecture candidate of choice for high performance CPU applications [1–3], can also be extended for general purpose SoC applications by proper device optimization. We demonstrate superior, best-in-its-class performance to our knowledge, as well as multi-Vt flexibility for low-operating power (LOP) applications. By high-k/metal-gate (HK/MG) and process flow optimizations, significant drive current (ION) improvement and leakage current (IOFF) reduction have been achieved through equivalent oxide thickness (EOT) scaling and carrier mobility improvement. N-FinFET and P-FinFET achieve, when normalized to Weff (Weff=2xHf+Wf), ION of 1325 µA/µm and 1000 µA/µm at 1 nA/µm leakage current under VDD of 1 V, and 960 uA/um and 690 uA/um at 1 nA/um under Vdd of 0.8V, respectively. This FinFET transistor module is promising for a 32/28nm SoC technology.

A 65nm node strained SOI technology with slim spacer

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current.

Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography

For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate delay (CV/I) at low gate leakage of 20-40A/cm/sup 2/ have been achieved over previous leading-edge 45nm node version, while maintaining the same sub-threshold leakage (100nA//spl mu/m). 10 times reduction of the leakage can be further modulated by a virtual back-gate control. Fine patterning with line pitch of 90nm by immersion lithography is demonstrated, which features 0.183/spl mu/m/sup 2/ 6T-SRAM cell for 32nm node on-trend scaling.

Strained FIP-SOI (finFET/FD/PD-SOI) for sub-65 nm CMOS scaling

A highly manufacturable SOI technology with strained silicon and FinFET-like devices is demonstrated for sub-65 nm device scaling. This technology, named FIP-SOI (FinFET/FD/PD-SOI), achieves (1) performance gain of 10-35% for N-MOS using strained silicon compared with non-strained SOI, (2) bulk-to-SOI design portability without additional structures such as the body-contacted transistor scheme, and (3) superior scalability by the incorporation of FinFET-like devices. All feature size scaling (gate length, channel width, and SOI body thickness) will further enhance channel strain in the FIP-SOI. Scaling-strengthened strain is demonstrated for the first time.

Scaling of CMOS FinFETs towards 10 nm

CMOS FinFETs with 35 nm gate length L/sub g/ and performance parameters exceeding that of ITRS projections are fabricated. Device simulations are performed to match the experimental results and to explore the scalability and optimization of FinFETs to 10 nm gate length. Symmetrical NMOS and PMOS V/sub t/s, low off-state leakages, and high drive currents can be realized using dual-doped poly-Si or mid-gap gate electrodes.

45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell

The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 /spl mu/A//spl mu/m for N-FET and P-FET, respectively. The P-FET current is the best reported so far.