Charbel J. Akl

Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion

Capacitive crosstalk between adjacent signal wires has significant effect on performance and delay uncertainty of point-to-point on-chip buses in deep submicrometer (DSM) VLSI technologies. We propose a hybrid polarity repeater insertion technique that combines inverting and non-inverting repeater insertion to achieve constant average effective coupling capacitance per wire transition for all possible switching patterns. Theoretical analysis shows the superiority of the proposed method in terms of performance and delay uncertainty compared to conventional and staggered repeater insertion methods. Simulations at the 90-nm node on semi-global METAL5 layer show around 25% reduction in worst case delay and around 86% delay uncertainty minimization compared to standard bus with optimal repeater configuration. The reduction in worst case capacitive coupling reduces peak energy which is a critical factor for thermal regulation and packaging. Isodelay comparisons with standard bus show that the proposed technique achieves considerable reduction in total buffers area, which in turn reduces average energy and peak current. Comparisons with staggered repeater which is one of the simplest and most effective crosstalk reduction techniques in the literature show that hybrid polarity repeater offers higher performance, less delay uncertainty, and reduced sensitivity to repeater placement variation.

Single-Phase SP-Domino: A Limited-Switching Dynamic Circuit Technique for Low-Power Wide Fan-in Logic Gates

The high switching activity of wide fan-in dynamic domino gates introduces significant power overhead that poses a limitation on using these compact high-speed circuits. This paper presents a new limited-switching clock-delayed dynamic circuit technique, called SP-Domino, which achieves static-like switching behavior, while maintaining the low-area and high-performance characteristics of wide fan-in dynamic gates. SP-Domino is a single-phase footless domino that can be freely mixed with static gates and can provide inverting and non-inverting functions. Simulations on 8 and 16 inputs or gates show that SP-Domino reduces dynamic power by up to 63% compared to same-UNG and same-delay standard footless domino, and up to 56.9% compared to low-contention high-speed standard footless domino.

An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition

This paper presents a power-gating structure that employs a staggered-phase damping technique for suppressing power and ground rails fluctuation and stabilization time during mode-transition. Two same type sleep devices coupled to two clusters in a single power domain are switched-on at different time instants such that the turn-on time of one of these is delayed by half the resonant oscillation period relative to the turn-on time of the other. The same can be generalized to plurality of clusters where one set of sleep devices switch at the first time instant and the other set switch at the said second time instant. This technique was evaluated in a 1-V 90-nm CMOS technology in the context of a 3-stage 16-bit Carry-Select-Adder (CSA) component, and compared with the parallel sleep transistor technique that is based on reducing the instantaneous excitation current. Results show that the present technique reduces peak noise by 33.2% compared to standard power-gating structure, and achieves a settling time reduction of 4.03× and 3.21× compared to standard and parallel sleep transistor power-gating structures, respectively.

Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects

Global signaling is becoming more and more challenging as technology scales down toward the deep submicron. We propose a new bus encoding technique, transition skew coding, that targets many of the global interconnects challenges such as crosstalk, peak energy and current, switching and leakage power, repeaters area, wiring area, signal integrity and noise. Simulations are done on different bus lengths using a 90nm library. Repeaters sizing and spacing are optimized, and the proposed encoded bus is compared against a standard bus and a bus with shields inserted between every two wires. The encoding and decoding latencies are also analyzed. Simulations show that transition skew coding is efficient in terms of energy and area with low encoding and decoding latency overhead.

Transition Skew Coding for Global On-Chip Interconnect

This paper presents new simulation results of the previously proposed transition skew coding (TSC) for global on-chip interconnects. Considering 2-GHz global clock frequency at the 90-nm node, we show that TSC can be applied to broad range of wire length on both semiglobal and global metal layers, while maintaining its energy efficiency and its advantages in terms of crosstalk reduction and signal integrity, and wiring and repeater area minimization.

Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion

Coupling capacitances between neighboring wires have a significant effect on performance and delay uncertainty of on-chip interconnects in deep submicron (DSM) technologies. We propose combining inverting and non-inverting repeater insertion to achieve a constant effective coupling capacitance for all possible input transitions. Unlike staggered repeater scheme, the increased wire resistance does not have any effect on our technique, and the performance is less sensitive to repeater placement variation. Simulations at the 90-nm node on a semi-global METAL5 layer show around 25% reduction in worst case delay and 86% delay uncertainty minimization

Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling

The continuous semiconductor technology scaling has made on-chip interconnect the major determinant of VLSI design cost and complexity. This necessitates the usage of signaling techniques that reduce the number of long on- chip wires and repeaters. In this paper, we present a point-to-point inter-block on-chip link design that allows simultaneous bidirectional signaling, thus reducing the number of signal lines and repeaters, while achieving high performance. By using accelerating repeaters and inserting a bidirectional latch at the midpoint of the link high performance simultaneous bidirectional signaling can be achieved with significant reduction in repeater and wire counts. We analyze the switching behavior of the proposed on-chip simultaneous bidirectional link (SBL) and find that it suffers from large switching activity overhead. Therefore, an opposite-polarity transition encoding is also proposed to reduce the power overhead of SBL without affecting its performance.

Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family

We present a new dynamic-like static circuit family called feedback-switch logic (FSL) that is suitable for high-speed low-power applications. FSL is a derivative of cascode voltage switch logic (CVSL) family. However, it does not suffer from the contention problems of clockless CVSL, and it consumes much less power than clocked CVSL (dual-rail domino). FSL gates offer fast switching, reduced capacitance, and input-switching dependent activity factor without the need of clock connection. An 18-bit majority voting circuit is simulated in a 90-nm technology, in order to compare static, clockless CVSL, dual-rail domino and FSL. Simulation results show that FSL reduces delay by 21% compared to static logic, and offers at least 46% power reduction compared to dynamic dual-rail domino logic with two-phase skew-tolerant clocking.

Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion

A simple yet effective technique that aims at reducing the energy and latency overheads incurred during the wakeup period of MTCMOS circuits is presented in this paper. One or more high-Vth keepers are inserted in MTCMOS combinational logic to reduce the metastability time that causes excessive short circuit current during mode transition and to minimize spurious glitches at internal circuit nodes. Employing the proposed keeper insertion technique in a 16-bit MTCMOS adder, up to 17.5% average wakeup energy and 54.6% wakeup latency reductions are achieved with negligible runtime power and latency overheads, while maintaining the standby energy efficiency of the original MTCMOS design.

Self-Sleep Buffer for Distributed MTCMOS Design

Leakage power is considered as major concern in deep sub-micrometer VLSI designs. MTCMOS technology was introduced to provide considerable power reduction in standby mode, while maintaining high performance in active mode. However, MTCMOS presents new challenges that require extra design effort. This paper targets the challenges and complexities related to sleep signal distribution in a distributed MTCMOS design. We propose synchronized dual-V,h self-sleep buffer method that eliminates the need for sleep signal distribution and allows easy implementation of MTCMOS wakeup scheduling. Guidelines for designing and sizing the self-sleep buffer circuit are provided. In a 90-nm technology and 2-GHz clock frequency, the self-sleep buffer consumes only 1.46- uWin active mode, while eliminating the sleep distribution network overheads and providing fast, low-energy active- to-standby-to-active transitions.