Charles E. Molnar

The counterflow pipeline processor architecture

The counterflow pipeline processor architecture (CFPP) is a proposal for a family of microarchitectures for RISC processors. The architecture derives its name from its fundamental feature, namely that instructions and results flow in opposite directions within a pipeline and interact as they pass. The architecture seeks geometric regularity in processor chip layout, purely local control to avoid performance limitations of complex global pipeline stall signals, and simplicity that might lead to provably correct processor designs. Moreover, CFPP designs allow asynchronous implementations, in contrast to conventional pipeline designs where the synchronization required for operand forwarding makes asynchronous designs unattractive. This paper presents the CFPP architecture and a proposal for an asynchronous implementation. Detailed performance simulations of a complete processor design are not yet available.

A FIFO ring performance experiment

We describe a high-speed FIFO circuit intended to compare the performance of an asynchronous FIFO with that of a clocked shift register using the same data path. The FIFO uses a pulse-like protocol to advance data along the pipeline. Use of this protocol requires careful management of circuit delays within its control circuits, as well as in the coordination of control signals with movement of bundled data. In simulations using hSpice, the throughput of the asynchronous circuit matches that of a two-phase clocked design. We fabricated 50 parts through MOSIS using their 0.6 micron design rules. We estimate from test measurements that the internal FIFO stages could support a maximum throughput from 930 million data items per second for the slowest of the 50 chips to 1126 million per second for the fastest chip. All 50 samples operated correctly as 3.3 V nominal Vdd varied from 1.67 V to over 4.8 V, with corresponding changes in operating speed and power as the supply voltage changed.