Mark A. Check

IBM's S/390 G5 microprocessor design

The IBM S/390 G5 microprocessor in IBMs newest CMOS mainframe system provides more than twice the performance of the previous generation, the G4. The G5 system offers improved reliability and availability, along with new architectural features such as support for IEEE floating-point arithmetic and a redesigned L2 cache and processor interconnect. The G5 system implements the ESA/390 instruction-set architecture, which is based on and compatible with the original S/360 architecture. Therefore, it has no RISC (reduced-instruction-set computing) concepts and is one of the most complex of all CISC (complex-instruction-set computing) architectures. Designers had to meet a unique set of challenges to achieve the G5s level of performance-for example, achieving a very high frequency given the complexity of the architecture.

Custom S/390 G5 and G6 microprocessors

Compared with the G4 microprocessor, the S/390® G5 microprocessor contains many architectural and performance enhancements. The G6 microprocessor represents a technology performance improvement over G5, with system support for additional processors. The G5 processor uses IBM CMOS 6X technology and has a clock frequency of 500 MHz in its fastest models. The G6 uses CMOS 7S technology with a clock frequency up to 637 MHz. The processors include a new IEEE binary floating-point architecture and additional reliability-availability-serviceability (RAS) improvements. The processor has significant performance improvements, including a larger level-1 (L1) cache, enhancements to the instruction fetch buffers, a branch target buffer (BTB), enhancements for a number of instructions, a new quiesce mechanism for instructions that modify translation lookaside buffer (TLB) entries, and a new level-2 (L2) cache and memory subsystem.

The microarchitecture of the IBM eServer z900 processor

The recent IBM ESA/390 CMOS line of processors, from 1997 to 1999, consisted of the G4, G5, and G6 processors. The architecture they implemented lacked 64-bit addressability and had only a limited set of 64- bit arithmetic instructions. The processors also lacked data and instruction bandwidth, since they utilized a unified cache. The branch performance was good, but there were delays due to conflicts in searching and writing the branch target buffer. Also, the hardware data compression and decimal arithmetic performance, though good, was in demand by database and COBOL programmers. Most of the performance concerns regarding prior processors were due to area constraints. Recent technology advances have increased the circuit density by 50 percent over that of the G6 processor. This has allowed the design of several performance-critical areas to be revisited. The end result of these efforts is the IBM eServer z900 processor, which is the first high-end processor based on the new 64-bit z/Architecture™.

IBM system z10 I/O subsystem

The performance, reliability, and functionality of a large server are greatly influenced by the design characteristics of its I/O subsystem. The critical components of the IBM System z10™ I/O subsystem have, therefore, been significantly improved in terms of performance, capability, and cost. The first-order network has been redesigned from the long-evolved enhanced self-timed interface (eSTI) links to utilize InfiniBand™ links. A redesign of the host logic of I/O chips and the fiberoptic interfaces within the links made it possible to introduce InfiniBand-based IBM Parallel Sysplex® links. A broad range of legacy I/O channels have been carried forward to connect through InfiniBand, and a foundation has been laid for new channel types of improved functionality and performance. The first such hardware channel to be introduced is the next generation of Ethernet-virtualization data routers. A new and methodical recovery structure has been designed to ensure consistent, extensive support of reliability, availability, and serviceability. A building-block-oriented design process has been developed to enable the innovations that made these advances possible. Finally, a new performance verification methodology has been introduced to ensure that the system and subsystem designs are balanced to make effective use of the increased capacity.

The next generation of highly reliable and secure encryption for the IBM z13

New business opportunities for cloud, analytics, mobile, and social applications depend on a secure computing infrastructure. The introduction of the IBM 4767 cryptographic coprocessor continues IBM leadership in marketplace security. The IBM 4767/Crypto Express5S is a versatile solution, offering three modes of operations on the IBM z13™ System: 1) Accelerator, 2) Common Cryptographic Architecture (CCA) Coprocessor, and 3) Enterprise PKCS #11 (public-key cryptography standard) Coprocessor. The highly programmable cryptographic coprocessor environment features a new ASIC (application-specific integrated circuit), FPGA (field-programmable gate array), and enhanced performance. The innovative internal hardware and firmware can be easily updated to achieve new security standards and requirements as well as new customer-specific functionality. The secure APIs (application programming interfaces) are designed to support standard cryptographic functions as well as specialized banking and financial functions. This is done in a way that allows the sensitive key material never to be exposed outside the physical secure boundary in a clear format. Performance benefits include the incorporation of elliptic curve cryptography (ECC) and format preserving encryption (FPE) in the hardware. For the z13, the number of logical domains has been increased from 16 to 85, allowing more system versatility. This new design also supports SRIOV (single root I/O virtualization) and the ability to customize arbitration to target SRIOV or quality of service.