Manar El-Chammas

A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration

This paper presents a 12-GS/s 5-bit time-interleaved flash ADC realized in 65-nm CMOS. To improve the dynamic performance at high input frequencies, a statistics-based background calibration scheme for timing skew is employed. The timing skew is detected in the digital domain through a correlation-based algorithm and minimized by adjusting digitally controlled delay lines. In order to minimize power consumption, we employ near minimum size comparators, whose offset is reduced through foreground calibrated trim-DAC circuitry. With the timing calibration activated, the skew-related impairments are reduced by 12 dB at high input frequencies, resulting in an SNDR of 25.1 dB near Nyquist. The prototype IC consumes 81 mW from a 1.1 V supply, yielding a figure-of-merit of 0.35 pJ/conversion-step at low input frequencies, and 0.46 pJ/conversion-step for inputs near Nyquist.

General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs

Time-interleaved analog-to-digital converters (TIADC) are sensitive to various mismatches that distort the sampled signal. Standard TIADC analysis assumes a sinusoidal input, which may result in pessimistic matching constraints for system-specific ADCs used with wideband input signals. Closed-form expressions bounding the acceptable phase-skew for wideband systems are derived, and are validated through simulations. In one of the examples presented it is shown that standard analysis can overconstrain the bound on acceptable phase-skew variance by a factor of three.

A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC

Pipelined ADCs designed in analog BiCMOS technologies can offer good linearity and high SNR performance for input signals with reasonable voltage swings. Such ADCs, however, face two critical design challenges: the process limits the sampling rate, and the pipeline architecture limits power efficiency. This paper introduces a two-way time-interleaved (TI) switched-current 1Gs/s 12b pipelined ADC in SiGe BiCMOS that addresses these issues.

General analysis on the impact of phase-skew in time-interleaved ADCs

Time-interleaved analog-to-digital converters (TIADCs) are sensitive to various mismatches that distort the sampled signal. Standard TIADC analysis assumes a narrowband sinusoidal input, which may result in pessimistic matching constraints for system-specific ADCs used with wideband input signals. Closed-form expressions bounding the acceptable phase-skew for wideband systems are derived and are validated through simulations. In one of the examples presented, it is shown that standard analysis can overconstrain the bound on acceptable phase-skew variance by a factor of three.

A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC

This paper describes a 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T&H to improve the dynamic performance of the individual sub-ADCs and to reduce both the converter error rate and the complexity of the required interleaving background calibration algorithms. It achieves an SFDR of 79 dBc and 66 dBc at low and high frequency inputs, respectively and an error rate of less than 10-9, and has a power consumption of 1.15 W for the core ADC.

15.8 90dB-SFDR 14b 500MS/S BiCMOS switched-current pipelined ADC

The authors present a single-channel 14b 500MS/s switched-current pipelined ADC that does not require background calibration, targeted for wireless infrastructure. The ADC achieves over 90dB SFDR and 64.8dB SNR at low frequency and over 80dB SFDR up to 500MHz, while consuming 550mW. It is implemented in a 0.18μm SiGe BiCMOS technology and is used in a quad-channel IC with serialized outputs. To achieve this linearity and sample rate combination without interleaving or calibration, we introduce several circuit techniques that reduce the T&H distortion, extend the available amplifier settling time, and enhance the ADC linearity at smaller signal amplitudes.

Time-Interleaved ADCs

In this chapter, a model for time-interleaved ADCs is presented. Frequency domain analysis is used to illustrate how time-varying errors, such as gain, offset, and timing skew, affect the resulting time-interleaved ADC output. Expressions relating the different errors to ADC performance and bounds on the magnitude of these errors are also derived for wide-sense stationary (WSS) signals, and simulations are used to demonstrate the accuracy of these expressions. Thus, for the given set of ADC specifications required by serial links, these expressions can be used to calculate the acceptable timing skew, such that it does not limit the performance of the time-interleaved ADC.

Voltage domain correction technique for timing skew errors in time interleaved ADCs

A voltage domain correction technique is proposed to mitigate the timing skew errors in time interleaved (TI) analog to digital converters (ADCs). The proposed technique exploits the fact that any timing skew in the sampling edge of a clock results in a corresponding error in sampled voltage that propagates through the ADC. The technique intends to cancel this voltage error by applying a correction voltage at the input sampling network in a TI-ADC. The effectiveness of the technique is demonstrated by using behavioral models of a 14-bit 500MS/s 2 channel TI-pipelined-ADC.

A 12 bit 1.6 GS/s BiCMOS 2×2 hierarchical time-interleaved pipeline ADC

A 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process is presented. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T/H to improve the dynamic performance of the individual sub-ADCs and to reduce both the complexity of the required interleaving background calibration algorithms and the error rate. It achieves an SFDR of 79 dBc at low frequency inputs and 66 dBc at Nyquist, and has an error rate of less than 10-9.

Mitigation of Timing Skew

In this chapter, sources of timing skew are discussed, and it is shown that the resulting timing skew is detrimental for ADCs with high-speed input signals. A statistics-based background calibration algorithm which mitigates the effect of timing skew is then presented with analysis on the various aspects of the algorithm. The chapter concludes with some of the requirements on the input signal such that the algorithm functions properly.