Charles Roberts Moore

IBM second-generation RISC machine organization

A highly concurrent second-generation RISC (reduced-instruction-set computer) that combines a powerful RISC architecture with sophisticated hardware design techniques to achieve a short cycle time and a low cycles-per-instruction (CPI) ratio is described. Like earlier RISC processors, this design uses a register-oriented instruction set, the CPU is hardwired rather than microcoded, and it features a pipelined implementation. Unlike earlier RISC processors, however, several advanced architectural and implementation features are used, including separate instruction and data caches, zero-cycle branches, multiple-instruction dispatch, and simultaneous execution of fixed- and floating-point instructions. The CPU has a four-word data bus to main memory, a four-word instruction-fetch bus from the I-cache arrays, and a two-word data bus between the D-cache and floating-point unit. The CPU has a full 64-b floating-point engine, and thirty-two 64-b floating point registers in addition to thirty-two 32-b fixed-point registers. In a single cycle, four instructions can be executed simultaneously.<<ETX>>

IBM single chip RISC processor (RSC)

A highly integrated single-chip microprocessor is described that combines a powerful RISC architecture and superscalar machine organization with system design optimizations appropriate for low cost workstation applications. This RISC single-chip (RSC) processor can dispatch up to two instructions per cycle and concurrently execute up to three instructions per cycle. The design integrates a fixed-point execution unit, a floating-point execution unit, an in-page branch unit, an 8-Kbyte unified cache, a memory management unit, a DMA controller, an interrupt controller, ECC on the memory interface, a real-time clock and decrementer, built-in self-test, and a versatile engineering support processor interface on a single die.<<ETX>>

Technology synergy for real system performance

Summary form only given, as follows. The rate of technological advancement and innovation surrounding the computer industry is enormous. Although the exponential gains in semiconductor density and performance are widely observed, the specific implications and opportunities represented by them are the subject of much debate. Similarly, although there has been large amount of innovation and progress in improved architectural concepts, parallelizing compilers, memory performance, system-level robustness, multiprocessor system design, and microprocessor machine organization, the appropriate balance point of these concepts is also the subject of much debate. This paper examines aspects of several key technology progressions, and connects the opportunities represented by them with the goal of demonstrating improved technology synergy for real system performance. As part of this discussion, the idea of real system performance is examined from several different angles. While it is clear that raw processing capability is a first order performance consideration, the specific of balance of optimization across the range of system parameters is an equally important consideration for real performance. In addition, although other system characteristics such as compatibility, upgradability, control, management, and robustness do not contribute directly to raw performance, they do play an important role in the delivery of real system performance as seen by the customer. Furthermore, in many cases, the same technology that opens up opportunities at one level also opens up weaknesses at another level. The idea of technology synergy works to balance these considerations.