Chun-Yi Liu

Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver

In this paper, a Golay-correlator window-based noise cancellation (GC-WNC) technique with frequency-domain equalizer (FDE) is proposed. The GC-WNC is a cooperative scheme in the time and frequency domains to combat the multipath effect in nonline-of-sight (NLOS) and LOS channels for orthogonal frequency-division multiplexing (OFDM) and single-carrier mode baseband inner receiver over 60-GHz environment for IEEE 802.15.3c and 802.11ad. According to mean-square error criterion, WNC approach is to minimize the estimation error between the ideal and the estimated channel frequency response (CFR) on each subchannel. The CFR is precisely obtained as coefficients of FDE to compensate multipath effect even in NLOS channel. The GC-WNC FDE with 8X-parallelism is designed as a part of digital baseband inner receiver with 40-nm CMOS general-purpose process. Because of area restriction of tape-out chip, only the OFDM mode is fabricated in the chip. The GC-WNC FDE has an equivalent gate count of 230k occupying 11.3% of the baseband inner receiver. Based on the chip measurement results, the baseband inner receiver with GC-WNC FDE provides 24-Gb/s throughput with 500-MHz operating clock and 0.94 V supply voltage. The power consumption of GC-WNC FDE is 69.79 mW. The baseband inner receiver with GC-WNC FDE can deliver a multigigabit per second throughput with the power dissipation of 2.91/2.26 mW/Gb/s at 500-/330-MHz operating clock for the OFDM mode.

A 802.15.3c/802.11ad dual mode phase noise cancellation for 60 GHz communication systems

In this paper, a phase noise cancellation (PNC) architecture is presented for 60 GHz communication systems. The BER performance is severely degraded by the non-ideal carrier frequency in 60 GHz bandwidth, which causes both common phase error (CPE) and residual carrier frequency offset (RCFO). The proposed simplified two-stage CPE algorithm solves the RCFO and common phase nose in the frequency domain and eliminates the constellation rotation on each sub-channel. Two-stage architecture together with deep pipelining technique achieves a high throughput rate. This PNC architecture has been implemented in a SC/OFDM Dual-Mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40 nm process. The proposed PNC is able to support 64QAM/16QAM for OFDM/SC mode, and can achieve up to 19.2 Giga-bit per second (Gbps) throughput rate at 400 MHz operating frequency with power consumption of 33 mW and area of 0.142 mm2.

Dual-Mode All-Digital Baseband Receiver With a Feed-Forward and Shared-Memory Architecture for Dual-Standard Over 60 GHz NLOS Channel

In this paper, an 8X-parallelism all-digital baseband receiver is proposed to support SC and OFDM modes for both IEEE 802.15.3c and IEEE 802.11ad standards. The all-digital baseband receiver contains a 4-in-1 synchronization (SYNC), a 512-point radix-23 IFFT/FFT, a phase noise cancellation (PNC), a shared memory (MEM) bank and a frequency-domain equalizer (FDE) with an optimized golay-correlator window-based noise cancellation (OGC-WNC) channel estimation (CE) for non-line-of-sight (NLOS) and line-of-sight (LOS) channels. The hardware sharing is 99% between SC and OFDM modes and the shared memory reduces memory usage by 51%. The measurement results show that the fabricated chip can provide PHY data rate of 9.24 Gb/s with power consumption of 497 mW to meet the requirement of OFDM mode for IEEE 802.15.3c and 802.11ad standards. Besides, the PHY data rate of the fabricated chip reaches 14 Gb/s with power consumption of 698 mW for OFDM mode that is beyond the standard requirement to offer higher PHY data rate over 60 GHz transmission environment.

A memory access reordering polyphase network for 60 GHz FBMC-OQAM baseband receiver

In this paper, a novel memory access reordering polyphase network (PPN) for 60 GHz filter bank multi-carrier (FBMC) offset QAM (OQAM) baseband receiver is presented. The 8X-parallelism architecture of PPN is integrated into our 8X-parallelism digital baseband receiver. The PPN is designed based on IEEE 802.15.3c and IEEE 802.11ad standards. The PPN contains three key modules including memory bank, filter coefficient selector and 4-tap PPN filter. The proposed PPN is synthesized with 40 nm 1P9M general purposes (GP) process. The implementation result shows it can operate at specified 330/500 MHz clock rate with power consumption of 17/26 mW at 0.81 V supply voltage. With 8X-parallelism architecture, the sampling rate supports up to 2.64/4 GHz.

An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver

Filter bank multi-carrier (FBMC) is a kind of new waveform that is an important topic in 5th generation wireless systems (5G). In this paper, we propose a novel memory access reordering polyphase network (PPN) for FBMC offset QAM (OQAM) system at 60 GHz band. The novel PPN architecture has lower complexity than the state-of-the-art designs, and it can be used in any FBMC-OQAM baseband design. To evaluate the system performance and hardware complexity of baseband receiver in millimeter wave (mmW) band, the proposed PPN is integrated into our 8X-parallelism 60 GHz band baseband receiver. The out-of-band (OOB) radiation in fixed-point simulation has 25 dB improvement as compared with OFDM. Furthermore, the transmission efficiency of FBMC-OQAM baseband receiver can improve 52% due to using more data subcarriers and removal of cyclic prefix (CP). The proposed PPN is synthesized with 40 nm 1P9M general purposes (GP) process, and can operate at 330/500 MHz clock rate with power consumption of 17/26 mW, providing the maximum PHY data rate up to 21.4 Gb/s.

A 802.15.3c/802.11ad compliant 24 Gb/s FFT processor for 60 GHz communication systems

This paper, we present a 24 Gb/s 512-point 8X-parallel FFT processor for 60 GHz communication systems. The proposed design is a pipelined Multipath Delay Feedback (MDF) radix-23 architecture, which exploits the parallelism of the multipath scheme together with pipeline technique to achieve a high throughput rate. Besides, the proposed FFT processor is implemented with an area efficient optimized multiplier architecture that avoid the need to store the twiddle factor in memory and a dynamic scaling technique to enhance the SQNR, allowing the FFT to operate with 16-QAM and 64-QAM for single carrier (SC) and orthogonal frequency-division multiplexing(OFDM) schemes. This FFT processor has been implemented in a SC/OFDM dual-mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40nm CMOS process. The post-layout implementation results show that the proposed FFT processor is able to achieve up to 24 Gb/s throughput rate at 500MHz clock with a power consumption of 87mW and area of 0.64mm2.

A CORDIC-based VLSI array for computing 2D discrete Hartley transform

The inseparability of the 2D discrete Hartley transform (DHT) makes its VLSI design and hardware realization much more expensive. To solve this problem, a new CORDIC-based 2D DHT algorithm and the associated array design are presented. By exploiting the CORDIC (coordinate rotations digital computer) property, the row/column decomposition can be successfully applied to reduce the computational complexity enormously without paying decomposition overhead. The array features systolic computing style, the CORDIC structure of processing elements (PEs), low input/output (I/O) cost, and simple hardware.<<ETX>>

Residual sampling clocking offset estimation and compensation for FBMC-OQAM baseband receiver in the 60 GHz band

In this paper, we propose a tracking mechanism for the residual sampling clocking offset (SCO) with corresponding pilot and auxiliary pilot arrangements for filter bank multi-carrier (FBMC) offset QAM (OQAM) baseband receiver in the 60 GHz band. This work can effectively compensate the non-ideal effects on the high-band subcarriers while using more data subcarrier for increasing bandwidth efficiency. This work is designed based on IEEE 802.15.3c and IEEE 802.11ad standards and synthesized with 40 nm 1P9M general purposes (GP) process. The proposed SCO tracking module with the proposed alternated pilot and auxiliary pilot arrangement can improve the BER floor and reach to 10−2 at SNR of 22 dB which is only 1.75 dB more than that of no SCO effect in 64-QAM modulation.

A MMSE Joint Feedback Feed-forward Equalizer for FBMC-OQAM Baseband Receiver in the 60 GHz Band

In this paper, a minimum mean square error (MMSE) joint feedback feed-forward equalizer (MJFFE) is proposed to deterministically suppress the inter-symbol interference and inter-carrier interference that arose from the filter bank multi-carrier in a long multipath channel of the 60-GHz indoor wireless transmission. The decision device is discarded in the decision feedback loop to reduce error propagation while at the same time applying the MMSE criterion to prevent over compensation influenced by additive white Gaussian noise. As a result, in an non-line-of-sight (NLOS) channel with 7.65-ns rms delay spread, a 3-tap MJFFE provides 3-dB improvement at the bit error rate (BER) 10−2 crossing and improve error floor effect at the BER 10−3 crossing, as compared with the 1-tap zero-forcing equalizer. Furthermore, the proposed equalizer coefficients calculation based on linear convolution for the MJFFE is also presented. The hardware complexity achieves 50% reduction by using several methods including multiplexing, memory sharing, and computation element sharing.

A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm

We present a digital baseband ASIC for 60 GHz single-carrier (SC) transmission that is optimized for communication scenarios in which most of the energy is concentrated in the first few channel taps. Such scenarios occur for example in office environments with strong reflections. Our circuit targets close-to-optimum maximum-likelihood performance under such conditions. To this end, we show for the first time how a reduced-state-sequence-estimation algorithm can be realized for the 1760 MHz bandwidth of the IEEE 802.11ad standard. The equalizer is complemented in the frontend by a synchronization unit for frequency offset compensation as well as a Golay-sequence based channel estimator and in the backend by an low density parity check (LDPC) decoder. In 40nm CMOS we achieve a measured data rate of up to 3.52 Gb/s using QPSK modulation.