Chee-Kian Ong

A BIST scheme for on-chip ADC and DAC testing

In this paper we present a BIST scheme for testing on-chip A/D and D/A converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measuring the DNL and INL of the converters. We validate the scheme with software simulation-5% LSB (least significant bit) test accuracy can be achieved in the presence of reasonable analog imperfection.

A new sigma-delta modulator architecture for testing using digital stimulus

Sigma-delta modulators are commonly used in high-resolution analog-to-digital converters (ADCs). Testing this type of modulator requires a high-resolution test stimulus, which is difficult to generate. A new architecture for the modulator is proposed so that its performance can be determined using only digital test stimulus. This architecture does not need analog test stimuli, which is prone to distortion/noise while setting up the high-resolution modulator for testing. Simulation results show that this technique is capable of accurately determining the performance of a second-order sigma-delta modulator ADC.

Jitter spectral extraction for multi-gigahertz signal

In this paper, we propose a method for extracting the spectral information of a multi-gigahertz jittery signal. This method may utilize existing on-chip single-shot period measurement techniques to measure the multi-gigahertz signal periods for spectral analysis. This method does not require an external sampling clock, nor any additional measurement beyond existing techniques. Experimental results show that this analysis method can accurately estimate the amount and frequencies of periodic and random jitter of a multi-gigahertz signal.

Delta-sigma modulator based mixed-signal BIST architecture for SoC

This paper proposes a mixed-signal Built-In Self-Test (BIST) architecture based on a second-order delta-sigma modulator. This modulator, which incorporates a design-for-testability (DfT) circuitry, is capable of testing/characterizing itself using digital stimulus. This characteristic is attractive for implementing the modulator as an on-chip analog signal analyzer. When applied for mixed-signal BIST, the modulator-based analog signal analyzer is first characterized using digital stimulus. Then the analyzer is utilized to characterize the stimulus generator in the BIST application. Some critical implementation issues of the BIST architecture are also discussed.

BER estimation for serial links based on jitter spectrum and clock recovery characteristics

High performance serial communication systems often require the bit error rate (BER) to be at the level of 10/sup -12/ or below. The excessive test time for measuring such a low BER is a major hindrance in testing communication systems cost-effectively. We propose a new technique for accurate and efficient estimation of the BER. The proposed technique estimates the BER based on the spectral information of jitter and the characteristics of the clock and data recovery circuit. The method can significantly reduce the production test time for BER testing. Simulation results demonstrate the potential usefulness of the method.

A scalable on-chip jitter extraction technique

In this paper, we propose a method for extracting the spectral information of a multi-gigahertz jittery signal. This method utilizes existing on-chip single-shot period measurement techniques to sample and measure the period of multiple cycles of the multi-gigahertz periodic signal for spectral analysis. Since measurements are made on the period of multiple cycles, but not on the period of a single cycle, a lower-speed timing measurement circuitry can be used to measure a higher-speed signal. Therefore, the proposed solution is scalable for even higher-speed signals. This method does not require an external sampling clock, nor any additional measurement beyond existing techniques. Experimental results based on simulation show that this method can accurately estimate the sinusoidal and random jitters of a multi-gigahertz signal.

Self-testing second-order delta-sigma modulators using digital stimulus

Single-bit second-order delta-sigma modulators are commonly used in high-resolution ADCs. Testing this type of modulator requires a high-resolution test stimulus, which is difficult to generate. This paper proposes a novel and robust technique to determine the performance of the modulator, which incorporates simple design-for-testability circuitry. This technique requires only digital stimulus to test the modulator. Hence, it is suitable as an analog signature analyzer used in built-in self-test applications. Simulation results show that this technique is capable of accurately determining the performance of a second-order delta-sigma modulator ADC.

Testing second-order delta–sigma modulators using pseudo-random patterns

Abstract Single-bit second-order delta–sigma modulators are commonly used in high-resolution analog-to-digital converters (ADCs). This type of modulator requires high-resolution test stimulus, which is difficult to generate. This paper proposes a novel and robust technique to determine the performance of the modulator by characterizing its key parameters using a pseudo-random pattern sequence. This technique is suitable for BIST application since a pseudo-random sequence can be generated on-chip using LFSR. Numerical simulation results show that this technique is capable of identifying parameters that affect the performance of a second-order delta–sigma modulator ADC.

Characterization of a pseudo-random testing technique for analog and mixed-signal built-in-self-test

In this paper, we characterize and evaluate the effectiveness of a pseudo-random-based implicit functional testing technique for analog and mixed-signal circuits. The analog test problem is transformed into the digital domain by embedding the device-under-test (DUT) between a digital-to-analog-converter and an analog-to-digital converter. The pseudo-random testing technique uses band-limited digital white noise (pseudo-random-patterns) as input stimulus. The signature is constructed by computing the cross-correlation between the digitized output response and the pseudo-random input sequence. We have implemented a DSP-based hardware testbed to evaluate the effectiveness of the pseudo-random testing technique. Our results show that we can achieve close to 100% yield and fault coverages by carefully selecting only two cross-correlation samples. Noise level and total harmonic distortion below 0.1% and 0.5%, respectively, do not affect the classification accuracy.

Bit-Error-Rate Estimation for High-Speed Serial Links

High-performance serial communication systems often require the bit error rate (BER) to be at the level of 10-12 or lower. The excessive test time for measuring such a low BER is a major hindrance in testing communication systems. In this paper, we show that the jitter spectral information extracted from the transmitted data and some key characteristics of the clock and data recovery (CDR) circuit can be used to estimate the BER effectively without comparing each captured bit for error detection. This analysis is also useful for designing a CDR circuit for systems whose jitter spectral information is known. Experimental results comparing the estimated and measured BER on a 2.5-Gb/s commercial CDR circuit demonstrate the high accuracy of the proposed technique