Dongwoo Hong

Jitter spectral extraction for multi-gigahertz signal

In this paper, we propose a method for extracting the spectral information of a multi-gigahertz jittery signal. This method may utilize existing on-chip single-shot period measurement techniques to measure the multi-gigahertz signal periods for spectral analysis. This method does not require an external sampling clock, nor any additional measurement beyond existing techniques. Experimental results show that this analysis method can accurately estimate the amount and frequencies of periodic and random jitter of a multi-gigahertz signal.

BER estimation for serial links based on jitter spectrum and clock recovery characteristics

High performance serial communication systems often require the bit error rate (BER) to be at the level of 10/sup -12/ or below. The excessive test time for measuring such a low BER is a major hindrance in testing communication systems cost-effectively. We propose a new technique for accurate and efficient estimation of the BER. The proposed technique estimates the BER based on the spectral information of jitter and the characteristics of the clock and data recovery circuit. The method can significantly reduce the production test time for BER testing. Simulation results demonstrate the potential usefulness of the method.

An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing

This paper describes a technique for estimating total jitter that, along with a loopback-based margining test, can be applied to test high speed serial interfaces. We first present the limitations of the existing estimation method, which is based on the dual-Dirac model. The accuracy of the existing method is extremely sensitive to the choice of the fitting region and the ratio of deterministic jitter to random jitter. Then, we propose a high-order polynomial fitting technique and demonstrate its value for a more efficient and accurate total jitter estimation at a very low Bit-Error-Rate level. The estimation accuracy is also analyzed with respect to different numbers of measurement points for fitting. This analysis shows that only a very small number (i.e., 4) of measurement points is needed for achieving accurate estimation.

A scalable on-chip jitter extraction technique

In this paper, we propose a method for extracting the spectral information of a multi-gigahertz jittery signal. This method utilizes existing on-chip single-shot period measurement techniques to sample and measure the period of multiple cycles of the multi-gigahertz periodic signal for spectral analysis. Since measurements are made on the period of multiple cycles, but not on the period of a single cycle, a lower-speed timing measurement circuitry can be used to measure a higher-speed signal. Therefore, the proposed solution is scalable for even higher-speed signals. This method does not require an external sampling clock, nor any additional measurement beyond existing techniques. Experimental results based on simulation show that this method can accurately estimate the sinusoidal and random jitters of a multi-gigahertz signal.

Bit-Error-Rate Estimation for High-Speed Serial Links

High-performance serial communication systems often require the bit error rate (BER) to be at the level of 10-12 or lower. The excessive test time for measuring such a low BER is a major hindrance in testing communication systems. In this paper, we show that the jitter spectral information extracted from the transmitted data and some key characteristics of the clock and data recovery (CDR) circuit can be used to estimate the BER effectively without comparing each captured bit for error detection. This analysis is also useful for designing a CDR circuit for systems whose jitter spectral information is known. Experimental results comparing the estimated and measured BER on a 2.5-Gb/s commercial CDR circuit demonstrate the high accuracy of the proposed technique

An efficient random jitter measurement technique using fast comparator sampling

This paper describes a random jitter measurement technique using simple algorithms and comparator sampling. The approach facilitates using automated test equipment (ATE) to validate devices with multiple, high-speed serial interfaces. The approach combines partial measurements based on individual data edge regions, in contrast to more common approaches that effectively first accumulate data from multiple edge regions. Random jitter is measured accurately even in the presence of deterministic and low-frequency periodic jitter, up to a cutoff frequency.

Random jitter extraction technique in a multi-gigahertz signal

In this paper, we propose a simple technique for estimating the standard deviation of a Gaussian random jitter component in a multi-gigahertz signal. This method may utilize existing on-chip single-shot period measurement techniques to measure the multi-gigahertz signal periods for the estimation. This method does not require an external sampling clock, or any additional measurement beyond existing techniques. Experimental results show that this extraction method can accurately estimate the random jitter variance in a multi-gigahertz signal even with the presence of a few hundred-hertz sinusoidal jitter components.

A two-tone test method for continuous-time adaptive equalizers

This paper describes a novel test method for continuous-time adaptive equalizers. This technique applies a two-sinusoidal-tone signal as stimulus and includes an RMS detector for testing, which incurs no performance degradation and a very small area overhead. To validate the technique, the authors used a recently published adaptive equalizer as the test case and conducted both behavioral and transistor-level simulations. Simulation results demonstrate that the technique is effective in detecting defects in the equalizer, which might not be easily detected by the conventional eye-diagram method

Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links

Clock and data recovery (CDR) circuits incorporating a bang-bang (BB) phase detector have been widely adopted in high-speed serial links due to their advantages in high speed implementations. However, the heavily non-linear nature of the BB phase detector makes the analysis of the CDR loop difficult. In this paper, we propose a new technique for accurate and efficient estimation of the bit- error rate (BER) for BB CDR circuits. The technique estimates the BER based on the spectral information of jitter and the jitter transfer characteristics of the BB CDR circuit. It eliminates the conventional BER measurement process and, thus, substantially accelerates the jitter tolerance test. In addition, this technique offers insights into the behavior of the non-linear CDR loop and the contribution of the jitter to the BER. We present simulation results that demonstrate the potential usefulness of the method.

Efficient Test Methodologies for High-Speed Serial Links

Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques.