Gao Hai-Xia

Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process

N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET. These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.

Resistive switching characteristics of Ti/ZrO2/Pt RRAM device

In this paper, the bipolar resistive switching characteristic is reported in Ti/ZrO2/Pt resistive switching memory devices. The dominant mechanism of resistive switching is the formation and rupture of the conductive filament composed of oxygen vacancies. The conduction mechanisms for low and high resistance states are dominated by the ohmic conduction and the trap-controlled space charge limited current (SCLC) mechanism, respectively. The effect of a set compliance current on the switching parameters is also studied: the low resistance and reset current are linearly dependent on the set compliance current in the log—log scale coordinate; and the set and reset voltage increase slightly with the increase of the set compliance current. A series circuit model is proposed to explain the effect of the set compliance current on the resistive switching behaviors.

A novel Monte-Carlo method for FPGA architecture research

A new Monte-Carlo-based approach is proposed for FPGA architecture research. Uniform open faults are randomly produced in the routing resource; and then interconnections are routed around obstacles. It does not depend on CAD algorithms and benchmark circuits. An example of switch block topology evaluation shows one can capture the same conclusion as that of CAD methods and shorten run-time from 15 hours to 15 minutes.

The Theoretical Investigation and Analysis of High-Performance ZnO Double-Gate Double-Layer Insulator Thin-Film Transistors

A novel structure of a ZnO thin-film transistor with a double-gate and double-layer insulator is proposed to improve device performance. Compared with the conventional ZnO thin-film transistor structure, the novel thin-film transistor has a higher on-state current, steeper sub-threshold characteristics and a lower threshold voltage, owing to the double-gate and high-k dielectric. Based on two-dimensional simulation, the potential channel distribution and the reasons for the improvement in performance are investigated.

The Anomalous Effect of Interface Traps on Generation Current in Lightly Doped Drain nMOSFET's

The anomalous phenomenon of generation current IGD in the lightly doped drain (LDD) nMOSFET measured under the drain bias VD-step mode is reported. We propose an assumption of activated (A) and frozen (F) traps for the VD-step mode: The A traps contributes to IGD while the F process can make them lose the roles as generation centers. The A and F regions can form the F-A region. The comparison of the F and A regions decides the role of the F-A region. The experiments confirm the assumption.