Chen-Huan Chiang

A novel fault injection method for system verification based on FPGA boundary scan architecture

A novel fault injection (a.k.a. fault insertion) method to facilitate the development of high quality system test is presented in this paper In this method, we utilize the existing boundary scan (BS) architecture of an FPGA to inject a hardware fault condition at any pin of the FPGA on a circuit board. Existing user-defined instructions of most FPGA BS architectures and the newly proposed design of their corresponding user-defined scan registers (USRs) constitute the proposed fault injection architecture. No new instruction, and no modification of the existing test access port (TAP) controller and BS registers are required. In addition, it is possible to reconfigure where and what type of faults to be injected asynchronously via the BS architecture while the system is online. Although the proposed method incurs at least additional delay through a multiplexer on the pin where a fault is injected, the programmability of an FPGA enables us to add fault injection logic only to where fault injection function is desired. Hence, area overhead and performance impact can be significantly reduced.

A practical approach to comprehensive system test & debug using boundary scan based test architecture

In this paper, we present a boundary scan based system test approach for large and complex electronic systems. Using the multi-drop architecture, a test bus is extended through the backplane and the boundary scan chain of every board is connected to this test bus through a gateway device. We present a comprehensive system test method using this test architecture to achieve high quality, reliability and efficient diagnosis of structural defects and some functional errors. This test architecture enables many advanced test methods like, embedded test application for periodic system maintenance, high quality backplane test for efficient diagnosis of structural defects on the backplane, in-system remote programming of programmable devices in the field. Finally, we present a novel fault injection method to detect and diagnose various functional errors in the system software of an electronic system. These methods were implemented in various systems and we present some implementation data to show the effectiveness of these advanced test methods.

End-to-end testing for boards and systems using boundary scan

ICs with IEEE 1149.1 boundary scan (BS) Architecture have been widely used in board level design to increase the testability. An end-to-end test methodology that utilizes BS architecture for testing boards and systems throughout the product life cycle is proposed. The proposed test methodology includes a programmable dynamic BS test architecture and a series of test modules that take advantage of the test architecture for complete fault coverage. Proposed design-for-testability (DFT) techniques guarantee the co-existence of BS resting with other system functions, such as in-system programming and DSP JTAG emulation. At board level, programmable dynamic scan chains are used in a divide-and-conquer fashion to increase the flexibility in the development phase (or design verification testing, DVT). Besides, since the DFT techniques are programmable they can be used as design-for-diagnosis to increase diagnosis resolution during DVT. Address scan port chips are used to enable multi-drop test bus architecture for backplane testing as well as system embedded testing. Other advanced techniques, such as analog subsystem testing and board-level built-in self-test, as well as how to re-use BS architecture in in-circuit testing and manufacture testing are also parts of the proposed methodology that takes advantage of BS architecture to provide full scale testing for systems.

Problems Using Boundary-Scan for Memory Cluster Tests

Boundary-scan testing is used to overcome many of the testability issues facing todays higher density designs. In the past, boundary-scan has been used successfully to perform interconnect testing between boundary-scan supporting devices. There has been an increased use of testing clusters of non-boundary-scan devices that are surrounded by boundary-scan access at the edge of the circuit both in manufacturing and system test. Boundary-scan is also being used to perform cluster testing of memory devices that do not support boundary-scan directly. These specialized boundary-scan tests are written to emulate a functional test pattern flow which requires a relatively precise control of the timing constraints in a synchronous clock window for synchronous dynamic random access memory (SDRAM). New interface architectures are also stressing the timing constraints available from a boundary-scan based test. This paper discusses the issues impeding boundary-scan based memory testing and suggests some alternative methods for testing these memory devices when boundary-scan testing is unattainable.