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Dive into the research topics where Tapan Jyoti Chakraborty is active.

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Featured researches published by Tapan Jyoti Chakraborty.


international test conference | 2007

A practical approach to comprehensive system test & debug using boundary scan based test architecture

Tapan Jyoti Chakraborty; Chen-Huan Chiang; B.G. Van Treuren

In this paper, we present a boundary scan based system test approach for large and complex electronic systems. Using the multi-drop architecture, a test bus is extended through the backplane and the boundary scan chain of every board is connected to this test bus through a gateway device. We present a comprehensive system test method using this test architecture to achieve high quality, reliability and efficient diagnosis of structural defects and some functional errors. This test architecture enables many advanced test methods like, embedded test application for periodic system maintenance, high quality backplane test for efficient diagnosis of structural defects on the backplane, in-system remote programming of programmable devices in the field. Finally, we present a novel fault injection method to detect and diagnose various functional errors in the system software of an electronic system. These methods were implemented in various systems and we present some implementation data to show the effectiveness of these advanced test methods.


asian test symposium | 2005

Efficient Test Architecture based on Boundary Scan for Comprehensive System Test

Tapan Jyoti Chakraborty

As electronic systems are becoming more complex with higher performance and require higher reliability, system test is becoming a very challenging task. Traditionally, functional test has been used to detect various design and manufacturing defects for electronic systems. However, functional test doesn’t work efficiently for large and complex systems specially when debugging and diagnosis of failure conditions is targeted. Boundary scan based test technology is being used for testing circuit boards in the industry for over a decade after being standardized by IEEE. This technology provides an access path to all the pins on all boundary scan-able chips on a circuit board.


Archive | 1998

Bist architecture for detecting path-delay faults in a sequential circuit

Sudipta Bhawmik; Tapan Jyoti Chakraborty; Nilanjan Mukherjee


Archive | 1994

Delay testing of high-performance digital components by a slow-speed tester

Vishwani D. Agrawal; Tapan Jyoti Chakraborty


Archive | 2003

Fault injection method and system

Tapan Jyoti Chakraborty; Chen-Huan Chiang


Archive | 2007

Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing

Tapan Jyoti Chakraborty; Chen-Huan Chiang; Suresh Goyal; Michele Portolan; Bradford Gene Van Treuren


Archive | 2008

APPARATUS AND METHOD FOR ISOLATING PORTIONS OF A SCAN PATH OF A SYSTEM-ON-CHIP

Tapan Jyoti Chakraborty; Chen-Huan Chiang; Suresh Goyal; Michele Portolan; Bradford Gene Van Treuren


Archive | 2007

Method and apparatus for describing parallel access to a system-on-chip

Tapan Jyoti Chakraborty; Chen-Huan Chiang; Suresh Goyal; Michele Portolan; Bradford Gene Van Treuren


Archive | 2007

Method and apparatus for describing and testing a system-on-chip

Tapan Jyoti Chakraborty; Chen-Huan Chiang; Suresh Goyal; Michele Portolan; Bradford Gene Van Treuren


Archive | 1999

Method and system for testing cluster circuits in a boundary scan environment

Tapan Jyoti Chakraborty; Bradford Gene Van Treuren

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