Chen Junning

A 1.2V High Linearity Mixer Design

This paper introduces double balance active mixer which is designed by Barrie Gilbert, it shows good characteristics in linearity, gain and isolation. In 1998, Barrie Gilbert present multi-tanh principle with bipolar transistors. So this paper uses the multi-tanh technique to design some new structure in order to improve linearity and gain. First we double the transconductor level with four NMOS transistors, then we tripled the transconductor level with six NMOS transistors, meanwhile we keep the circuit is symmetry. Using Cadence SpectreRF, the circuits show better linearity and gain, yet noise figure increase, so it exists a tradeoff among these parameters of active mixer. In this paper, the circuit simulated in 2.4 GHz down-conversion mixer with 0.18 mum process, IIP3 and ldB compression point achieved 8.5 dBm and 2 dBm, gain is 4 dB, power assumption is 6 mW. Although this new architecture being used in down conversion mixer, it can be applied in up conversion active mixers too.

An improved resonant parametric perturbation for chaos control with applications to control of DC/DC converters

This paper presents an improved resonant parametric perturbation method based on the modulation of a nonlinear map for controlling chaos. The control target can be any periodic orbit, which is not necessarily what is embedded in the chaotic attractor. Application of the method is illustrated for a common current-programmed DC/DC converter which has been known to easily become chaotic for a wide parameter range. The control effects of chaos are demonstrated with computer simulations.

Analysis of self-heating effect and breakdown characteristics in partial SOI LDMOS with multi silicon windows

This paper proposes a novel partial SOI LDMOS with multi silicon windows. The two-dimensional numerical analysis is performed to investigate the self-heating effects and breakdown characteristics of partial SOI LDMOS. The PSOI devices with multi silicon windows overcome the disadvantages of the conventional PSOI devices and are shown to keep better balance between the self-heating effects and the breakdown voltage which can be optimized at the same time. Furthermore, the drive current and threshold voltage shift are improved during high-temperature operation effectively. The optimum design of structure for the provided design is also presented according to the synthetical simulations of its performances.

Unipolar resistive switching of Au+-implanted ZrO2 films

The resistive switching characteristics of Au+-implanted ZrO2 films are investigated. The Au/Cr/Au+-implanted-ZrO2/n+-Si sandwiched structure exhibits reproducible unipolar resistive switching behavior. After 200 write-read-erase-read cycles, the resistance ratio between the high and low resistance states is more than 180 at a readout bias of 0.7 V. Additionally, the Au/Cr/Au+-implanted-ZrO2/n+-Si structure shows good retention characteristics and nearly 100% device yield. The unipolar resistive switching behavior is due to changes in the film conductivity related to the formation and rupture of conducting filamentary paths, which consist of implanted Au ions.

A CMOS Low Voltage High Linear Down Conversion Mixer Design

Based on traditional Gilbert Cell prototype, a 900 MHz down-conversion mixer which conclude class AB transconductor and LC tank is demonstrated in this paper. The RF, LO and IF port frequencies are 900 MHz, 800 MHz and 100 MHz, respectively. With SMIC 0.18 um process, simulation results show -1.2 dBm of P-ldB compression point and 8.5 dBm of IIP3 with -5 dBm LO power and 1.2 V supply voltage.

A circuit macromodel of high voltage LDMOS based on numerical simulation

Lateral double-diffused MOSFET (LDMOS) is widely used in power integrated circuits and microwave integrated circuits. So creating equivalent circuit of LDMOS is becoming more important. The previous models divided the on-state region of LDMOS into two parts, linear region and saturation region. The formulas and equivalent circuits are very complicated. This paper presents an I-V equation that is available in the whole on-state region by numerical simulation, and creates a macromodel of LDMOS circuits. The model contains fewer parameters that are easily extracted. Then we obtain a simpler equivalent circuit. Convergence becomes easier when using this equivalent circuit to simulate power integrated circuits. In the end, we give an application of our model.

The process and performance of double doping polysilicon gate MOSFET

In early days, our project team has analyzed the electric field, threshold voltage, capacitance, cut-off frequency and other characteristics of the double doping polysilicon gate MOSFET (DDPG-MOS), see references [1]. In this study, the process steps of DDPG-MOS are designed and simulated with software TSUPREM. Then the frequency and transient characteristic of the device are analyzed using software MEDICI. The results show that, the process of DDPG-MOS is completely compatible with CMOS, and its performances are improved significantly. Specially, DDPG-MOS has a wider frequency range and faster response speed, which has good application prospects in the RF field.

A simple and accurate method for measuring program/erase speed in a memory capacitor structure

With the merits of a simple process and a short fabrication period, the capacitor structure provides a convenient way to evaluate memory characteristics of charge trap memory devices. However, the slow minority carrier generation in a capacitor often makes an underestimation of the program/erase speed. In this paper, illumination around a memory capacitor is proposed to enhance the generation of minority carriers so that an accurate measurement of the program/erase speed can be achieved. From the dependence of the inversion capacitance on frequency, a time constant is extracted to quantitatively characterize the formation of the inversion layer. Experimental results show that under a high enough illumination, this time constant is greatly reduced and the measured minority carrier-related program/erase speed is in agreement with the reported value in a transistor structure.

A New Design of Voltage Controlled Oscillator

This paper designed a new low phase noise voltage- controlled oscillator (VCO) with harmonic filtering resistor and source damping resistor. The author analyzed and modulated the results by the simulator of Mentor Graphics in a 0.35-um CMOS process, and achieved the optimization scheme in the end. The simulation result shows the VCO can reach a phase noise of - 124.9 dBc/Hz at 1 MHz offset while working at 4.6 GHz in a 3 mA excursion current. During the 0 to 3 controlled voltage the tuning range can reach 18.5%, and the power consumption is only 7.09 mW.

A 1.2V High Performance Mixer for 5.8GHz WLAN Application

Based on traditional Gilbert Cell prototype, a 5.8 GHz down-conversion mixer which conclude CMOS gm Cell and LC tank is demonstrated in this paper. The RF, LO and IF port frequencies are 5.8 GHz, 5.75 GHz and 50 MHz, respectively. With SMIC 0.18 um process, simulation results show 3.2dB of conversion gain,-0.8dBm of P-1dB compression point and 7.9 dBm of IIP3 with -5dBm LO power and 1.2 V supply voltage.