Ke Daoming

Analysis of self-heating effect and breakdown characteristics in partial SOI LDMOS with multi silicon windows

This paper proposes a novel partial SOI LDMOS with multi silicon windows. The two-dimensional numerical analysis is performed to investigate the self-heating effects and breakdown characteristics of partial SOI LDMOS. The PSOI devices with multi silicon windows overcome the disadvantages of the conventional PSOI devices and are shown to keep better balance between the self-heating effects and the breakdown voltage which can be optimized at the same time. Furthermore, the drive current and threshold voltage shift are improved during high-temperature operation effectively. The optimum design of structure for the provided design is also presented according to the synthetical simulations of its performances.

A circuit macromodel of high voltage LDMOS based on numerical simulation

Lateral double-diffused MOSFET (LDMOS) is widely used in power integrated circuits and microwave integrated circuits. So creating equivalent circuit of LDMOS is becoming more important. The previous models divided the on-state region of LDMOS into two parts, linear region and saturation region. The formulas and equivalent circuits are very complicated. This paper presents an I-V equation that is available in the whole on-state region by numerical simulation, and creates a macromodel of LDMOS circuits. The model contains fewer parameters that are easily extracted. Then we obtain a simpler equivalent circuit. Convergence becomes easier when using this equivalent circuit to simulate power integrated circuits. In the end, we give an application of our model.

A modeling of parasitic capacitances between gate and the source/drain for a high-k dielectric gate MOSFET

This paper proposes a two-dimensional boundary value problem for a high-k gate dielectric MOSFET and its sidewall spacer oxide. We have calculated the two-dimensional electrical potential distribution and charge distribution. A model of parasitic capacitance between the gate and the source/drain for a MOSFET has been given. In this paper, we also analyze the relationship between these parasitic capacitances and geometry dimension parameters with a semi-analytical method. The results show that there is a smallest parasitic capacitance by changing the magnitude of gate dielectric constant. The accuracy of the method is tested by comparing the modeled results with CST (computer simulation technology) simulation results. Satisfactory agreement is observed between calculation results of the model and the prediction made by CST.

Compact model of surface potential in strong inversion channel

In this work, the expression of surface potential corresponding to strong inversion state is presented which is distinct from the classical value 2VB due to quantum effect. Then threshold voltage is calculated and it is found that quantum effect affects seriously threshold voltage.

An analytical model for the output voltage of four-terminal silicon pressure transducers

The paper resolved a two-dimensional partial differential equation of transverse piezoresistive effect transducers with the method of perturbation. Relationship between the output voltage and device size has been gotten. We verified that the maximum output voltage is located at the middle point of output terminal. And then the expression of the maximum output voltage is given. The calculation results are accordant with numerical and experimental values of devices. These expressions based on the paper can be used in designs and simulations of four-terminal piezoresistive pressure transducers