Cheng-Chieh Chang

CMOS analog divider and four-quadrant multiplier using pool circuits

CMOS divider and four-quadrant multiplier circuits using the pool circuits are presented. Using CMOS differential amplifiers and MOS transistors biased in the saturation region, the new analog divider and multiplier are presented. Experimental and simulation results are given-to verify the theoretical analyses. The proposed circuits are expected to be useful in analog signal processing applications. >

Pseudo-exponential function for MOSFETs in saturation

In this paper, according to the Taylors series expansion, two pseudo-exponential circuits were realized. The proposed circuits provide a simple method to synthesize pseudo-exponential circuits. Both of the circuits were composed of MOS transistors operating in saturation. One of the pseudo-exponential function circuits is voltage-mode and was tested using discrete components. The other one is current-mode, which is verified with the 0.8 /spl mu/m CMOS process by Hspice simulations. The results confirm the feasibility of the proposed circuits.

Active-R sinusoidal oscillators using the CFA pole

Three new sinusoidal oscillators using ihe curreni feedback amplifier (CFA) pole are presented. Two of the proposed sinusoidal oscillators consist of CFAs and resistors without external capacitances. Their oscillation condition and frequency can be independently controlled by two resistors. Experimental results were given lo demonstrate the feasibility of the proposed circuits. The proposed circuits will be suitable for high-frequency applications and integration in bipolar monolithic lechnology.

A CMOS square-law vector summation circuit

A CMOS vector summation circuit using the square-law characteristics of MOS transistors in the saturation region is presented. Simulation and experimental results are given to verify the theoretical analyzes. Second-order effects such as mobility reduction and transistor mismatch are also investigated. The proposed circuits are expected to be useful in analog signal-processing applications.

New CMOS four-quadrant multiplier and squarer circuits

A CMOS four-quadrant multiplier and a squarer using the positive feedback loops consisting of the current mirrors are presented. Simulation results are given to verify the theoretical analysis. The input range of this multiplier is over ±2.5V with the linearity error less than 1% and its-3dB bandwidth is about 20MHz. The total harmonic distortion is less than 1% with the input range up to ±2V. The squarer has a ±1.6V input range. Second order effects such as mobility reduction and transistor mismatch have been discussed. Experimental results by using discrete components are also given. The proposed circuits are expected to be useful in analog signal-processing applications.

Low-Voltage BiCMOS Four-Quadrant Multiplier and Squarer

A new low-voltage low-power BiCMOS four-quadrant multiplier using cascode NPN and NMOS pairs is presented. This circuit has been fabricated in a 1 μm BiCMOS process. Experimental results show that for a power supply of ±1.5 V, the linear range is over ±0.8 V with the linearity error less than 2%. The total harmonic distortion is less than 2% with input range up to ±0.8 V. The measured −3 dB bandwidth of the proposed multiplier is about 10 MHz. Its static power dissipation is about 50 μW. The squarer modified from the proposed multiplier has the input range up to ±1 V. This circuit is expected to be useful in low-voltage analog signal processing applications.

Low-Voltage Analog Tripler Circuit

A new low-voltage CMOS tripler is presented in this paper. It is realized by the square-law characteristics of MOS transistors operating in saturation. The proposed circuit has been fabricated in a 0.8 μm CMOS process. Experimental results have been given to demonstrate the feasibility of the proposed circuit. It is expected to be useful in low-voltage analog signal-processing applications.

Low-voltage BiCMOS four-quadrant multiplier using triode-region transistors

A low-voltage BiCMOS four-quadrant multiplier using triode-region transistors is presented, this circuit has been fabricated in a 1.0 /spl mu/m BiCMOS process. Experimental results show that for a power supply of /spl plusmn/1.5 V, the linear range is over /spl plusmn/0.6 V with the linearity error of less than 2%. The total harmonic distortion is less than 2% with an input range up to /spl plusmn/0.6 V. The measured -3-dB bandwidth of this proposed BiCMOS multiplier is about 10 MHz. This circuit is expected to be useful in low-voltage analog signal-processing applications.