Cheng Huang

A low-power high-speed true single phase clock divide-by-2/3 prescaler

A novel low power high-speed true single-phase clockbased (TSPC) divide-by-2/3 prescaler is presented. By modifying the precharge branch in the TSPC flip-flop instead of the AND gate in conventional topologies, the inverter between the two flip-flops of the conventional divide-by-2/3 prescaler is eliminated, and the number of switching stages is reduced to 6. The prescaler is designed in SMIC 0.18 μm CMOS process, the simulating results show that the maximum operating frequency of the prescaler in divide-by-3 mode reaches 10 GHz with 1.836 mW power consumption, and is 50% faster than the conventional divide-by-3 circuit. The maximum operating frequency of the prescaler in divide-by-2 mode reaches 8 GHz with 1.34 mW power consumption.

A CMOS Switched Load Harmonic Rejection Mixer for DTV Tuner Applications

In this paper, a switched load harmonic rejection mixer (HRM) structure with one single mixer core and a pair of switched load resistors is proposed. Different from the traditional three-phase HRM which is widely used in DTV tuners, this HRM performs the harmonic rejection function by vector multiplication rather than superposition. Sharing most of its parts with an ordinary Gilbert mixer, the proposed HRM shows greater simplicity in structure. The single mixer-core structure is also more power efficient than a traditional three-phase HRM. In order to verify the effectiveness of this approach, a proof-of-concept prototype is designed and fabricated in 0.18- μm RFCMOS technology. Measurements indicate that 38 dB for 3rd and 34.5 dB for 5th harmonic rejection ratio can be achieved. The HRM including a buffer stage consumes a low bias current of 3 mA under 1.8 V supply voltage and has equivalent performance such as CG, NF, and IIP3 to an ordinary Gilbert mixer. With the load switch inactivated, this HRM can be easily transformed into an ordinary Gilbert mixer, which increases its flexibility for different applications.

Built-in self-test structure for fault detection of charge-pump phase-locked loop

A defect-oriented built-in self-test (BIST) structure of charge-pump phase-locked loop (CP-PLL) for high fault coverage and low area overhead test solution is proposed. It employs a new structure of phase/frequency detector, a D flip-flop and some existing blocks in the PLL as the input stimulus generator and fault feature extracted devices for testing evaluation. Thus, no extra test stimulus or high-performance measured instruments are required for test. The structure is easily implemented and has a little influence on the performance of CP-PLL. Fault simulation results indicate that the proposed BIST structure has high fault coverage (98.75%) and low area overhead (0.78%).

A 2.4-GHz All-Digital PLL With a 1-ps Resolution 0.9-mW Edge-Interchanging-Based Stochastic TDC

A 2.4-GHz all-digital phase-locked loop (ADPLL) for Zigbee application is presented. A stochastic time-to-digital converter (STDC) with an edge-interchange circuit (EIC) is proposed. The rising edges of the two input clocks of STDC are cyclically interchanged by EIC, which achieves dynamic element matching and doubles the equivalent number of arbiters in STDC. The frequency resolution of the LC-based digitally controlled oscillator is improved by the tiny unit capacitor and the high-speed dithering. The proposed ADPLL has been implemented in a 0.13-μm CMOS technology. The measurement results show a 9-mW total power consumption, in which the proposed 1-ps-resolution STDC only consumes 0.9 mW. The in-band and out-band phase noise are -83.0127 dBc/Hz at 10 kHz and -118.95 dBc/Hz at 1 MHz. The root-mean-square jitter and peak-to-peak jitter are 4.6 and 25.7 ps, respectively.

A high-resolution DCO with MOS capacitors

A digitally controlled oscillator (DCO) that achieves a minimum frequency tuning step of 20 kHz without any dithering is presented. Three tuning stages are employed to obtain a wide frequency range of 1 GHz in the classical LC tank. The fine tuning bank is realized by inverse connection of two pairs of pMOS transistors and a tiny unit capacitance of 0.47 fF is achieved. A prototype integrated in 130nm CMOS technology exhibits a phase noise of -118.7 dBc/Hz @1MHz offset and a power dissipation of 2 mW under a supply of 1.2 V. The core area size is 330um×480um.

On the use of multi-tone for the measurement of noise power ratio distortion in RF circuits

This paper is aimed to propose a noise power ratio (NPR) measurement method with fewer tones than traditionally used. Accurate measurement of NPR distortion is achieved by averaging distortion power measured at the notch frequency excited by multi-tone signals with different random phases. Automatic measurement software is developed to perform all NPR measurement procedures. Measurement results show that the variance is below 0.4 dB after averaging 100 NPR distortions excited by 60-tone. Compared to the NPR measurement results obtained by a more-typical 10000-tone stimulus, the measurement error is 0.23 dB using only 60-tone signals with average.

A newly high-speed equalizer for QAM signals

A new algorithm SGD-CMA for QAM signals in high-speed equalizer is presented in this paper. SGD-CMA integrates conventional CMA and DD-LMS under stop-and-go principle. The SGD-CMA equalizer performs six times faster, with 3~5 dB better in rudimental MSE, more rapidly on capturing the channel variety than conventional CMA and almost the same error rate characteristic, while decreasing 82% of operation complexity and increasing 5% of hardware consumption. MATLAB simulations support SGD-CMA on all performance and characteristics, validating its feasibility and advantages. Finally using CMOS 0.18 mum library to synthesis, the new equalizer is embedded into DVB-C demodulation chip, and chip test result shows that the performance of the new equalizer is better.

A Low Offset Dynamic Comparator with Offset Elimination Circuit

A new dynamic comparator with offset elimination circuit is proposed. The offset elimination circuit decreases the influence of the offset voltage effectively and increases the resolution of the comparator. The simulation results show that, if the pre-set offset voltage is 10mV, the offset elimination circuit can decrease to the enough low value, which meets the requirements of the system. The standard deviation of the offset voltage decreases from 7.27mV to 1.15mV with the utilization of the offset elimination circuit in Monte Carlo simulation.

A Review of LC-Based Digitally Controlled Oscillator with High Frequency Resolution

In 2003, a digitally controlled oscillator (DCO) for cellular mobile phones was first proposed and demonstrated, and after that DCOs are widely used along with the rapid development of wireless communications. DCOs based on LC structure gain an advantage over ring oscillators in phase noise and thereby become research hotspot during the last decade. This paper presents a review of inductance capacitance (LC)-DCOs classified by circuit topologies and performance. For each DCO structure, the principle exposition and performance analysis are given in detail. Moreover, a comparison among all kinds of DCOs mentioned in this paper is presented in tabular form. Finally, we discuss the obstacle to the development of DCOs and the possible tendency for future work in summary.

An ADPLL with a MASH 1-1-1 ΔΣ Time-digital converter

An all digital phase-locked loop with a frequency range of 2.35 ~ 2.55 GHz is presented. A MASH 1-1-1 ΔΣ time-digital converter is used to quantize phase errors. High resolution and third-order noise-shaping are achieved simultaneously. A digitally controlled oscillator with three-stage tuning bank is used to realize wide frequency range and high frequency resolution. A prototype integrated in 130nm CMOS process exhibits a phase noise of -122 dBc/Hz @1MHz offset at a frequency of 2.48 GHz and a power dissipation of 11 mW under a supply of 1.2 V. The core occupied 0.49 mm2 of area.