Fuqing Huang

A power reduction technique for multi-modulus divider

A new power reduction technique is presented for multi-modulus divider based on 2/3 divider cells. The ‘mod’ signals are employed to turn off the current of end-of-cycle logic blocks in 2/3 divider cells, when they have no contribution to the divider operation. An ideal multi-modulus divider adopting the power reduction technique is presented. Theory analyses show that the saved power percentage varies from 42.5% to 49% with division ratios changing from 256 to 8191 and the average saved power percentage is about 48.8%. As the division ratio becomes larger, the saved power percentage will be closer to 50%. An 11-bit multi-modulus divider based on this power reduction technique has been implemented in SMIC 0.18 um CMOS process. Theory analysis, simulation and test results show that the power reduction technique can save more than 39% power.

Wide division ratio range programmable frequency divider with close-to-50% output duty-cycle

A novel wide division ratio (DR) range programmable frequency divider is presented in this article, which is based on the proposed divide-by-2/3/4 cell. The dividers output is buffered by a divide-by-2 cell; hence, it can achieve the close-to-50% output duty-cycle. The DRs can be set via the convenient provisions of binary bits. When the DR is even, the output duty-cycle is exactly 50%. If the DR is odd, the output duty-cycle is k/(2 k + 1), where k is a natural number, therefore, it becomes close-to-50% with an increasing k. A divider with eight DR control bits, which can realise the DRs from 8 to 511, is implemented in standard 0.18 µm complementary metal-oxide semiconductor technology, the die area is 0.02 mm2. The measured results show that the divider can obtain 44.4–50% output duty-cycle which corroborates with the calculation.

Current reused Colpitts VCO and frequency divider with quadrature outputs

A low power current reused Colpitts VCO and divide-by-two circuit is proposed in 0.18µm CMOS technology. The divider is stacked on top of a common drain gm-boosted differential Colpitts VCO to share DC current. A capacitance neutralization technique is used to compensate the miller effect of the parasitic gate-drain capacitance Cgd in the VCO, and improves the generated negative resistance and phase noise performance. The Colpitts VCO works at 4.293-4.513GHz, and can provide 2.147-2.257GHz quadrature outputs through the stacked divide-by-two circuit. The VCO circuit exclude the output buffer consumes 2.8mA at 1.8V supply voltage. The measured phase noise is -109dBc/Hz at 1MHz offset frequency when the VCO output is 4.513GHz.

A CMOS voltage controlled oscillator topology for suppression of flicker noise up-conversion

A CMOS voltage controlled oscillator (VCO) topology is proposed to suppress the flicker noise up-conversion, thus improving its close-in phase noise performance. The idea is based on a previous work relying on insertion of resistors in series with the conducting channel resistors of the complementary cross coupled pairs. The immunity of the loaded quality factor (Q) to the conducting channel resistors which are modulated by their flicker noise is enhanced, thus reducing the flicker noise up-conversion gain. In the proposed topology, the VCO oscillation amplitude is not degraded and the resistance is never constrained by the threshold voltage, which are problems of the previous topology. Meanwhile the number of resistors is halved, lowering circuit complexity. Two VCOs based on the previous topology and the proposed topology are designed in a 65nm CMOS process. Simulation results show the phase noise of the proposed VCO is improved by more than 4dB at 1kHz offset frequency and 2dB at 10kHz offset frequency over the whole 2.85GHz to 3.75GHz tuning range.