Cheng-Liang Hung

A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique

This study demonstrates a 6-GHz triangular-modulated spread-spectrum clock generator (SSCG) based on a fractional-N PLL in a 90-nm CMOS process. This paper presents a phase-rotating technique to create the fractional-N topology for the SSCG and implement spread-spectrum clocking (SSC) by modulating the fractional-N ratios. The proposed phase-rotating technique consists of virtual multiphase generation and the phase compensation approach. This technique effectively compensates the instantaneous timing error and shows the ignorable quantization error. Unlike the delta-sigma technique commonly used for SSCGs, the proposed SSCG realizes non-dithered fractional division ratios. In terms of SSC, this approach suppresses the RMS jitter to less than 1 ps, showing a significant improvement in the jitter performance in this work. The measured power attenuation of electromagnetic interference (EMI) is 16.12 dB, with a deviation of less than 0.5% (5000 ppm). Operating at a 6-GHz clock rate, the measured RMS jitter with and without the down-spreading spectrum are 0.77 and 0.71 ps, respectively. The chip core area is less than 0.55 × 0.45 mm2 and the core power consumption is 27.7 mW at a supply of 1.0 V.

A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes

This study demonstrates a wide frequency tuning range LC voltage-controlled oscillator (LC-VCO) with an active inductor in a 90-nm CMOS process. As the proposed LC-VCO is intended to be extremely flexible without redesign for several new-generation SerDes interfaces, a wide operating frequency makes the phase-locked loop (PLL) applicable to the multistandards. To demonstrate a highly competitive design, a quality (Q) factor enhancement technique has been also demonstrated to reduce the loss from the active inductor, leading to an appropriate phase noise over the entire tuning range. At a supply of 1.2 V, the fabricated LC-VCO provides a frequency tuning range of 0.9-8 GHz (160%) with power consumption of 3.2-19.1 mW. The measured phase noise is from -105 to -118 dBc/Hz at a 1-MHz offset. Realized in a fully integrated PLL chip, it occupies an active area of 0.08 × 0.16 mm2.

Arbitrary Duty Cycle Synchronous Mirror Delay Circuits Design

An arbitrary duty cycle synchronous mirror delay (SMD) circuit is proposed in this paper. The conventional SMD can be locked in 2 clock cycles, but it just can accept only the narrow pulse clock signal, which will greatly restrict the application of the circuits. The modified TSPC DFF is used in the proposed SMD circuit to detect clock edge. Therefore, the proposed SMD circuit not only can be locked in 2 clock cycle time but also can accept arbitrary duty cycle clocks. Moreover, it can detect a small dead zone and makes the new circuit has better jitter performance and lower static phase error. An experiment chip was fabricated in 0.18 mum CMOS process. With a 1.8 V supply voltage, the measure results show that the proposed circuits can be operated from 450 MHz to 750 MHz. When the input clock frequency is 750 MHz, the measured power dissipation was 9 mW. In addition, the peak-to-peak and rms jitters were 24 ps and 2.94 ps, respectively.

A Sub-1V Low-Power High-Speed Static Frequency Divider

In this paper, a low-power high-speed static frequency divider is proposed. By utilizing the forward body-bias (FBB) technique and parallel switching topology which employ differential PMOS input pair, the proposed 2:1 static frequency divider can not only be operated at a supply voltage of 0.7V but also keep the structure of tail current source to provide constant current. The frequency divider is designed based on TSMC 0.18mum 1p6m CMOS process. The 2:1 frequency divider can be operated up to maximum operating frequency 10.18 GHz while consuming 1.68 mW from a supply voltage of 0.9V. As operating at supply voltage of 0.7V, the operating frequency is 4.07GHz and the power dissipation is 0.96mW.

A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III

In this paper, a 6GHz spread-spectrum clock generator (SSCG) for Serial AT Attachment Generations 3 (SATA-III) is presented. By utilizing frequency modulation which employs digital MASH delta-sigma modulator and 33KHz triangular profile address generator, the SSCG achieves an output clock of 6GHz and 5000ppm down spread with a triangular waveform. The SSCG was designed based on TSMC 0.13μm 1p8m CMOS process. The power dissipation is 48mW under a 1.2V supply voltage. The peak-to-peak jitter of non spread-spectrum clock is 8ps, and the EMI reduction is 15dB with normal frequency spread modulation from 6GHz to 5.97GHz.

A High Linearity and Fast-Locked PulseWidth Control Loop with Digitally Programmable Output Duty Cycle for Wide Range Operation

In this paper, a high linearity PWCL is proposed. By using the linear control stage and digital-controlled charge pump (DCCP), the proposed PWCL can be operated in wide range of input duty cycle and produced wide range of output duty cycle in wide frequency range. Utilizing simple detect circuit to control DCCP in complementary architecture, the proposed PWCL can reduce lock time ratio to 4.9. The test chip was fabricated in 0.18mum CMOS process. The measurement results show that the frequency range of input signal is from 50MHz to 1.3GHz, the duty cycle range of input signal is from 30% to 70% and the programmable duty cycle of output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8mW and 13.2ps respectively at an operation frequency of 1.3GHz

A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-µm CMOS technology

This study presents a 6-Gb/s clock and data recovery (CDR) for the high-speed data transmission systems. Similar to the concept of the oversampling CDR, the proposed CDR presents an alternative scheme, which uses the data delay window (DDW) and a sensing-amplified phase detector (SAPD) to substitute the conventional DFF-based PD. It shows that the NRZ data could be aligned and recovered by the only one clock instead of the multi-phase clock, and the complexity of the clock distribution network could be mitigated than counterpart. The study has been implemented in TSMC 0.13 um. Operating at the 6-Gb/s data rate and 3-GHz clock frequency, the estimated peak to peak jitter of the recovered clock is 7.55 ps, and the recovered data jitter is less than 6.4 ps. The core area of data recovery (DR) loop occupies 0.291 mm2. The core power consumption of the all loops including I/O buffer is around 50 mW at the supply voltage of 1.2V.

A 3 GHz spread-spectrum clock generator with a self-calibration technique

A spread-spectrum clock generator (SSCG) with self-calibration circuit (SCC) is presented in this paper. By the use of self-calibration scheme, exploited the proposed linear circuit and a SCC, the gain of Kvco can be effectively reduced and the jitter performance is improved. Moreover, the proposed architecture provides an alternative technique for low Kvco instead of the commonly used methods for voltage-control oscillator (VCO) calibration. The SCC-based SSCG ensures phase locking under the process, voltage and temperature (PVT) variations. For spread-spectrum clocking, the digital MASH delta-sigma modulator and a 33-kHz triangular addressor is used. The proposed SSCG generates an output clock of 3 GHz and approximate 5000-ppm down spreading with a triangular-modulated shape. The SSCG has been designed in TSMC 0.18 μm CMOS technology. Operating at a 3-GHz clock rate, the peak-to-peak jitter of non spread-spectrum is 3.85 ps. The electromagnetic interference (EMI) reduction is larger than 20 dB with a triangular-modulated frequency of 3–2.985 GHz.

A 0.06-ps RMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation

A 90-nm CMOS, 6-GHz spread-spectrum clock generator (SSCG) showing low jitter and the feasible electromagnetic interference (EMI) reduction is presented. Forsaking the commonly used ΔΣ technique for the average fractional-N ratios by the dithering, the proposed SSCG uses a phase-rotating technique to realize truly fractional division ratios, and creates the spread-spread clocking (SSC) by modulating the fractional-N ratios. The phase-rotating technique effectively calibrates instantaneous timing error and shows ignorable quantization error. Operating at a 6-GHz clock rate, the measured RMS jitter with and without a 0.5% (5000-ppm) down-spreading spectrum are 0.77 ps and 0.71 ps, respectively, showing a significant improvement in the suppressed sub-1ps RMS jitter and the mere increase in RMS jitter of 0.06 ps while implementing SSC. As the serial AT attachment (SATA) standard suggesting the 100 kHz-RBW for the instruments, the measured power attenuation of EMI is 16.12 dB under a 5000-ppm frequency deviation. The chip core area is less than 0.55 × 0.45 mm2, and the core power consumption is 27.7 mW at a 1.0-V supply.

A 3 GHz DLL-based clock generator with stuck locking protection

This study presents a 3-GHz DLL-based clock generator with stuck locking protection. In this paper, a proposed duty cycle corrector solves the problem of the sensitivity to half transparent (HT) architecture and the stuck locking error in the DLL simultaneously. Based on the frequency-multiplied technique, the multiphase DLL architecture synthesizes a 3-GHz output clock. The post-layout simulation results are based on TSMC 0.18 µm 1P6M CMOS process. The proposed architecture locks into the input frequency of 250 MHz. Operating at the 3-GHz frequency multiplier output, the simulated peak-to-peak jitter is 2.94 ps and 31.17 ps for the 250-MHz locked frequency and 3-GHz synthesized frequency, respectively. The chip area is less than 0.745 × 0.745 mm2 and the power consumption is 20.9 mW at a supply of 1.8 V.