Kuo-Hsing Cheng

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1–3], MRAM [4–5], and resistive RAM (RRAM) [6–8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (VBL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

Fast-Write Resistive RAM (RRAM) for Embedded Applications

Especially for microcontroller and mobile applications, embedded nonvolatile memory is an important technology offering to reduce power and provide local persistent storage. This article describes a new resistive RAM device with fast write operation to improve the speed of embedded nonvolatile memories.

A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip

A phase-locked loop (PLL) is proposed for low-voltage applications. A new charge pump (CP) circuit, using gate switches affords low leakage current and high speed operation. A low-voltage voltage-controlled oscillator (LV-VCO) composed of 4-stage delay cells and a low-voltage segmented current mirror (LV-SCM) achieves low voltage-controlled oscillator gain (KVCO), a wide tuning range, and good linearity. A LV-SCM generates more current with small area by switching the body rather than the gate. The PLL is implemented in standard 90-nm CMOS with regular VT (RVT) devices. Its output jitter is 2.22 ps (rms), which is less than 0.5% of the output period. The phase noise is - 87 dBc/Hz at 1-MHz offset from a 2.24-GHz center frequency. Total power dissipation at 2.24-GHz output frequency, and with 0.5-V power supply is 2.08 mW (excluding the buffers). The core area is 0.074 mm2.

A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation

A high linearity pulsewidth control loop (PWCL) is proposed in this paper. Using the linear control stage (CS) and digital-controlled charge pump (DCCP), the proposed PWCL can be operated within a wide-range of both input and output duty cycles over a wide frequency range. A simple detection circuit is utilized to control the DCCP in a complementary architecture such that the proposed PWCL can reduce the locking time ratio to 4.5. The test chip is fabricated using 0.18 mum CMOS process. The measurement results show that the frequency range of the input signal was 1 MHz to 1.3 GHz, the duty cycle range of the input signal is from 30% to 70% and the programmable duty cycle of the output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8 mW and 13.2 ps, respectively, at an operating frequency of 1.3 GHz.

A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator

This brief describes a fast-lock mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time-to-digital-converter scheme for a frequency-range selector and a coarse tune circuit to reduce the lock time. A multi-controlled delay cell for the voltage-controlled delay line is applied to provide the wide operating frequency range and low-jitter performance. The charge pump circuit is implemented using a digital control scheme to achieve adaptive bandwidth. The chip is fabricated in a 0.25-mum standard CMOS process with a 2.5-V power-supply voltage. The measurements show that this DLL can be operated correctly when the input clock frequency is changed from 32 to 320 MHz, and can generate ten-phase clocks within a single cycle without the false locking problem associated with conventional DLLs and wide-range operation. At 200 MHz, the measured rms random jitter and peak-to-peak deterministic jitter are 4.44 and 15 ps, respectively. Moreover, the lock time is less than 22 clock cycles. This DLL occupies less area (0.07 mm2) and dissipates less power (15 mW) than other wide-range DLLs.

A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop

In this paper, a dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loops is proposed and analyzed. The proposed topology is based on two tuning loops: a fine-tuning loop and a coarse-tuning loop. A coarse-tuning loop is used for fast convergence, and a fine-tuning loop is used to complete fine adjustments. The proposed phased-locked loop (PLL) circuit is designed based on the TSMC 0.35-/spl mu/m 1P4M CMOS process with a 3.3-V supply voltage. HSPICE simulation shows that the lock time of the proposed PLL can be reduced over 82% in comparison to the conventional PLL. An experimental chip was implemented and measured. The measurement results show that the proposed PLL has fast locking properties.

Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique

This brief describes an ultralow-voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultralow voltage. The chip is fabricated in a 0.13-mum standard CMOS process with a 0.5-V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610 MHz with a 0.5-V power supply voltage. At 550 MHz, the measured root-mean-square jitter and peak-to-peak jitter are 8.01 and 56.36 ps, respectively. The total power consumption of the PLL is 1.25 mW, and the active die area of the PLL is 0.04 mm2.

A high-accuracy and high-efficiency on-chip current sensing for current-mode control CMOS DC-DC buck converter

In this paper, a high accuracy, high efficiency, and wide current sensing range on chip current sensing technique is presented. The proposed current sensing circuit uses simple switch technique to achieve high accuracy. The current sensing circuit has no OP amplifier so that it would not reduce the power efficiency. The test chip is fabricated in TSMC 0.18 mum 1P6M 3.3 V CMOS process. The measurement results show that the buck converter with on-chip current sensing circuit can operate from 700 KHz to 1.4 MHz with supply voltage from 2.5 to 5 V for lithium ion battery application. The accuracy of proposed current sensing circuit is higher than 89.8% for load current from 50 to 500 mA and for temperature from 0 to 100degC. The power efficiency of the buck converter is up to 91.2%.

Design of current mode operational amplifier with differential-input and differential-output

In this paper, a CMOS implementation of a current operational amplifier (COA) with a differential input and a differential output is described. The amplifier is configured from a differential current mirror input transimpedance stage followed by a differential output transconductance gain stage. A differential mode design technique is proposed and used in the feedback circuit. This configuration is the current mode counterpart of the traditional voltage mode operational amplifier (VOA). In this design, the simulation results exhibit an open-loop differential gain of 51.71 dB with the gain-bandwidth product 314 MHz and a settling time of 14 ns.

The novel efficient design of XOR/XNOR function for adder applications

A new concept to implement high performance XOR/XNOR functions that using the pass transistor technique is proposed. It requires only six MOS transistors. Base upon this concept, a new high-speed full adder is proposed for low-power application. We used the modified Karnaugh map (K-map) method to obtain the various pass transistor circuits. We modified the Boolean expression to simplify the control and input signals of the pass transistor logic (PTL) to realize a one-bit full adder. The analysis of the proposed one-bit adders is compared with that of the static CMOS adder, the CPL transmission function adder, the DPL transmission gate adder, and the CPL transmission gate adder. The simulation results shows that the proposed new circuit has the lowest power delay product performance.