Wei-Bin Yang

Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique

This brief describes an ultralow-voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultralow voltage. The chip is fabricated in a 0.13-mum standard CMOS process with a 0.5-V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610 MHz with a 0.5-V power supply voltage. At 550 MHz, the measured root-mean-square jitter and peak-to-peak jitter are 8.01 and 56.36 ps, respectively. The total power consumption of the PLL is 1.25 mW, and the active die area of the PLL is 0.04 mm2.

The charge-transfer feedback-controlled split-path CMOS buffer

A new low-power high-speed CMOS buffer, called the charge-transfer feedback-controlled split-path (CFS) CMOS buffer, is proposed. By using the feedback-controlled split-path method, the short circuit current of the output inverter is eliminated. Four additional MOS transistors are used as the charge-transfer diodes, which can transfer the charge stored in the split output-stage driver to the output node. Thus the propagation delay and power dissipation of the CFS buffer are reduced. The HSPICE simulation results show that the power-delay product of the CFS CMOS buffer is a savings over 20% in comparison to a conventional CMOS tapper buffer at 100 MHz operation frequency.

High frequency characteristics of annealed Co-base amorphous alloy ribbons

The rapidly quenched amorphous Co‐base alloy CobalFe4Ni2Si15B14 (Metglas 2714A) is a suitable material for the magnetic core operating in a high frequency. Appreciable reduction in core loss and increase in permeability of this material can be achieved by proper heat treatment. In this study, data from differential scanning calorimetry (DSC) and high frequency magnetic properties of samples annealed at different temperatures is presented. The results show that magnetic core loss at 50 kHz and 0.4 T decreases as annealing temperature (Ta) increases from 400 to 753 K, and it reaches a minimum with an anomaly factor η of 1.5 at annealing temperature of 753 K. Initial permeability μi behaves more complicately and reach the maximum value of 24000 at the same temperature, which is 50 K lower than the crystallization temperature (Tx = 823 K). This improvement of high frequency magnetic properties is attributed to the presence of small nuclei precipitated during heat treatment. The fraction of crystalline part in...

Designing ultra-low voltage PLL Using a bulk-driven technique

This paper describes an ultra-low voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultra-low voltage. The chip is fabricated in a 0.13-µm standard CMOS process with a 0.5V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610MHz with a 0.5V power supply voltage. At 550MHz, the measured rms jitter and peak-to-peak jitter are 8.01ps and 56.36ps, respectively. The total power consumption of the PLL is 1.25mW and the active die area of PLL is 0.04mm2.

A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit

This paper describes a fully differential DLL-based frequency multiplier using a noise-rejected voltage-controlled delay line (VCDL). In order to improve the power consumption and synthesized frequency range of the DLL-based frequency multiplier, we design an edge combiner using current mode logic to generate a fully differential output clock. This edge combiner consists of four stage fully differential current logic with XOR scheme. It can obtain the characteristic of high speed operation. Based on TSMC 0.18/spl mu/m 1P6M N-well CMOS process, the simulation results show that the DLL can operate from 360 to 550MHz. And, the frequency multiplier can synthesize frequency from 720MHz to 2.2GHz. The proposed frequency multiplier produces the 2/spl times/ and 4/spl times/ fully differential output clock frequency. The total power dissipation is only 38mW and the cycle-to-cycle jitter is less than 17ps.

A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler

A new ultra low voltage dynamic floating input D flip-flop (DFIDFF) is proposed for high speed prescaler circuit. Prescaler and VCO are the main blocks that determining the speed of phase locked-loop (PLL). In this paper, a very low power-delay product divide-by 4/5 prescaler based on our DFIDFF is proposed. The prescaler implemented with 0.13 mum 1P8M N-well CMOS process with an ultra low 0.5 V power supply voltage. By HSPICE simulation results, the power-delay product (PDP) of the novel divided-by 4/5 prescaler can be reduced over 39% in comparison to conventional divided-by 4/5 prescaler. Moreover, the novel divided-by-4/5 prescaler circuit can operate at 613 MHz with the power consumption of 8.014 uW under a 0.5 V supply voltage.

A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III

In this paper, a 6GHz spread-spectrum clock generator (SSCG) for Serial AT Attachment Generations 3 (SATA-III) is presented. By utilizing frequency modulation which employs digital MASH delta-sigma modulator and 33KHz triangular profile address generator, the SSCG achieves an output clock of 6GHz and 5000ppm down spread with a triangular waveform. The SSCG was designed based on TSMC 0.13μm 1p8m CMOS process. The power dissipation is 48mW under a 1.2V supply voltage. The peak-to-peak jitter of non spread-spectrum clock is 8ps, and the EMI reduction is 15dB with normal frequency spread modulation from 6GHz to 5.97GHz.

A High Linearity and Fast-Locked PulseWidth Control Loop with Digitally Programmable Output Duty Cycle for Wide Range Operation

In this paper, a high linearity PWCL is proposed. By using the linear control stage and digital-controlled charge pump (DCCP), the proposed PWCL can be operated in wide range of input duty cycle and produced wide range of output duty cycle in wide frequency range. Utilizing simple detect circuit to control DCCP in complementary architecture, the proposed PWCL can reduce lock time ratio to 4.9. The test chip was fabricated in 0.18mum CMOS process. The measurement results show that the frequency range of input signal is from 50MHz to 1.3GHz, the duty cycle range of input signal is from 30% to 70% and the programmable duty cycle of output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8mW and 13.2ps respectively at an operation frequency of 1.3GHz

A low-power high-driving ability voltage control oscillator used in PLL

Modern high-speed CMOS processors using on-chip phase-locked loop (PLL) often require a clock buffer with stringent specifications on the rising time and falling time of the signal rather than on the delay time of the buffer. For these applications, we propose a novel low-power high-driving ability voltage controlled oscillator (LPVCO) used in PLL. The proposed LPVCO is based on the waveform-shaper and split-path CMOS driver techniques to reduce the short-circuit power dissipation and the area requirement than that achievable by the traditional PLL with tapered CMOS buffer. By Hspice simulation results, the power-frequency product of the LPVCO can be reduced by more than 15% in comparison to conventional VCO. Thus, the novel low-power high-driving ability VCO can be used in PLL.

The suggestion for CFS CMOS buffer

Two recent papers, one by Huang et al. (1996) and the other by Cheng et al. (1997), on the driver buffer are commented on. The feedback-controlled split-path CMOS buffer (FS) claims that the 4-split-path buffer can reduce the power and power-delay product. But the voltage of the gates in the output inverter stage is not enough to turn-off the PMOS transistor and the NMOS transistor. Due to this, charge-recovery must be used. The charge-transfer feedback-controlled split-path (CFS) CMOS buffer that has high-speed low-power performance by using transfer of the charge stored in the split output-stage driver to the output node. Thus the power-delay product can be reduced greatly by combining the technology described in the former two papers. The HSPICE simulation results show that the power-delay product of the suggested CMOS buffer is reduced by 20% to 40% in comparison to the conventional CMOS tapered buffer at 100 MHz operation frequency at heavy capacitive load.