Chenguang Qiu

Scaling carbon nanotube complementary transistors to 5-nm gate lengths

Moving transistors downscale One option for extending the performance of complementary metal-oxide semiconductor (CMOS) devices based on silicon technology is to use semiconducting carbon nanotubes as the gates. Qiu et al. fabricated top-gated carbon nanotube field-effect transistors with a gate length of 5 nm. Thin graphene contacts helped maintain electrostatic control. A scaling trend study revealed that, compared with silicon CMOS devices, the nanotube-based devices operated much faster and at much lower supply voltage, and they approached the limit of one electron per switching operation. Science, this issue p. 271 Carbon nanotube field-effect transistors approach the quantum limit of one electron per switching operation. High-performance top-gated carbon nanotube field-effect transistors (CNT FETs) with a gate length of 5 nanometers can be fabricated that perform better than silicon complementary metal-oxide semiconductor (CMOS) FETs at the same scale. A scaling trend study revealed that the scaled CNT-based devices, which use graphene contacts, can operate much faster and at much lower supply voltage (0.4 versus 0.7 volts) and with much smaller subthreshold slope (typically 73 millivolts per decade). The 5-nanometer CNT FETs approached the quantum limit of FETs by using only one electron per switching operation. In addition, the contact length of the CNT CMOS devices was also scaled down to 25 nanometers, and a CMOS inverter with a total pitch size of 240 nanometers was also demonstrated.

Carbon Nanotube Feedback-Gate Field-Effect Transistor: Suppressing Current Leakage and Increasing On/Off Ratio

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

Modularized Construction of General Integrated Circuits on Individual Carbon Nanotubes

While constructing general integrated circuits (ICs) with field-effect transistors (FETs) built on individual CNTs is among few viable ways to build ICs with small dimension and high performance that can be compared with that of state-of-the-art Si based ICs, this has not been demonstrated owing to the absence of valid and well-tolerant fabrication method. Here we demonstrate a modularized method for constructing general ICs on individual CNTs with different electric properties. A pass-transistor-logic style 8-transistor (8-T) unit is built, demonstrated as a multifunctional function generator with good tolerance to inhomogeneity in the CNTs used and used as a building block for constructing general ICs. As an example, an 8-bits BUS system that is widely used to transfer data between different systems in a computer is constructed. This is the most complicated IC fabricated on individual CNTs to date, containing 46 FETs built on six individual semiconducting CNTs. The 8-T unit provides a good basis for constructing complex ICs to explore the potential and limits of CNT ICs given the current imperfection in available CNT materials and may also be developed into a universal and efficient way for constructing general ICs on ideal CNT materials in the future.

Comparison of Mobility Extraction Methods based on Field-Effect Measurements for Graphene

Carrier mobility extraction methods for graphene based on field-effect measurements are explored and compared according to theoretical analysis and experimental results. A group of graphene devices with different channel lengths were fabricated and measured, and carrier mobility is extracted from those electrical transfer curves using three different methods. Accuracy and applicability of those methods were compared. Transfer length method (TLM) can obtain accurate density dependent mobility and contact resistance at relative high carrier density based on data from a group of devices, and then can act as a standard method to verify other methods. As two of the most popular methods, direct transconductance method (DTM) and fitting method (FTM) can extract mobility easily based on transfer curve of a sole graphene device. DTM offers an underestimated mobility at any carrier density owing to the neglect of contact resistances, and the accuracy can be improved through fabricating field-effect transistors with...

Transient response of carbon nanotube integrated circuits

The speed of frequency response of all published carbon nanotube (CNT) integrated circuits (ICs) is far from that predicted. The transient response of CNT ICs is explored systematically through the combination of experimental and simulation methods. Complementary field-effect-transistor (FET) based inverters were fabricated on a single semiconducting CNT, and the dynamic response measurement indicates that it can only work at an unexpectedly low speed, i.e. with a large propagation delay of 30 μs. Owing to the larger output resistance of CNT FETs, the existence of parasitic capacitances should induce much larger resistive-capacitive (RC) delay than that in Si ICs. Through detailed analysis combining simulation and experimental measurements, several kinds of parasitic capacitances dragging down the actual speed of CNT FET ICs are identified one by one, and each of them limits the speed at different levels through RC delay. It is found that the parasitic capacitance from the measurement system is the dominant one, and the large RC delay lowers the speed of CNT FETs logic circuits to only several kHz which is similar to the experimental results. Various optimized schemes are suggested and demonstrated to minimize the effect of parasitic capacitances, and thus improve the speed of CNT ICs.

Exploration of vertical scaling limit in carbon nanotube transistors

Top-gated carbon nanotube field-effect transistors (CNT FETs) were fabricated by using ultra-thin (4.5u2009nm or thinner) atomic-layer-deposition grown HfO2 as gate insulator, and shown to exhibit high gate efficiency, i.e., all examined (totally 76) devices present very low room temperature subthreshold swing with an averaged value of 64u2009mV/Dec, without observable carrier mobility degradation. The gate leakage of the CNT FET under fixed gate voltage is dependent not only on the thickness of HfO2 insulator, but also on the diameter of the CNT. The vertical scaling limit of CNT FETs is determined by gate leakage standard in ultra large scale integrated circuits. HfO2 film with effective oxide thickness of 1.2u2009nm can provide both excellent gate electrostatic controllability and small gate leakage for sub-5u2009nm FETs based on CNT with small diameter.

Performance projections for ballistic carbon nanotube FinFET at circuit level

A novel three-dimensional device structure for a carbon nanotube (CNT) fin field-effect transistor (FinFET) is proposed and evaluated. We evaluated the potential of the CNT FinFET compared with a Si FinFET at a 22-nm node at the circuit level using three performance metrics including propagation delay, total power dissipation, and energy-delay product (EDP). Compared with a Si FinFET, the CNT FinFET presents obvious advantages in speed and EDP arising from its almost much larger current density but also results in a higher total power dissipation, especially at a low threshold voltage (Vth = 1/3Vdd). A suitable improvement in Vth can effectively contribute to a significant suppression of leakage current and power dissipation, and then an obvious optimization is obtained in the EDP with an acceptable sacrifice in speed. In particular, CNT FinFETs with optimized threshold voltages can provide an EDP advantage of approximately 50 times over Si FinFETs under a low supply voltage (Vdd = 0.4 V), suggesting great potential for CNT FinFET-based integrated circuits.

Improving subthreshold swing to thermionic emission limit in carbon nanotube network film-based field-effect

In this letter, we explore the vertical scaling-down behavior of carbon nanotube (CNT) network film field-effect transistors (FETs) and show that by using a high-efficiency gate insulator, we can substantially improve the subthreshold swing (SS) and its uniformity. By using an HfO2 layer with a thickness of 7.3u2009nm as the gate insulator, we fabricated CNT network film FETs with a long channel (>2u2009μm) that exhibit an SS of approximately 60u2009mV/dec. The preferred thickness of HfO2 as the gate insulator in a CNT network FET is between 7u2009nm and 10u2009nm, simultaneously yielding an excellent SS (<80u2009mV/decade) and low gate leakage. However, because of the statistical fluctuations of the network CNT channel, the lateral scaling of CNT network film-based FETs is more difficult than that of conventional FETs. Experiments suggest that excellent SS is difficult to achieve statistically in CNT network film FETs with a small channel length (smaller than the mean length of the CNTs), which eventually limits the further sca...

Atomic-Layer-Deposition Growth of an Ultrathin HfO2 Film on Graphene

Direct growth of an ultrathin gate dielectric layer with high uniformity and high quality on graphene remains a challenge for developing graphene-based transistors due to the chemically inert surface properties of graphene. Here, we develop a method to realize atomic-layer-deposition (ALD) growth of an ultrathin high-κ dielectric layer on graphene through premodifying the graphene surface using electron beam irradiation. An amorphous carbon layer induced by electron beam scanning is formed on graphene and then acts as seeds for ALD growth of high-κ dielectrics. A uniform HfO2 layer with an equivalent oxide thickness of 1.3 nm was grown as a gate dielectric for top-gate graphene field-effect transistors (FETs). The achieved gate capacitance is up to 2.63 μF/cm2, which is the highest gate capacitance on a graphene solid-state device to date. In addition, the fabricated top-gate graphene FETs present a high carrier mobility of up to 2500 cm2/(V·s) and a negligible gate leakage current of down to 0.1 mA/cm2, showing that the ALD-grown HfO2 dielectric layer is highly uniform and of very high quality.

Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches

Cooler electrons for transistors The operating power of field-effect transistors is constrained in part by the minimum change in voltage needed to change the current output. This subthreshold swing (SS) limit is caused by hotter electrons from a thermal electron source leaking over the potential of the gate electrode. Qiu et al. show that graphene can act as a Dirac source that creates a narrower distribution of electron energies. When coupled to a carbon nanotube channel, the decrease in SS would allow the supply voltage to be decreased from 0.7 to 0.5 volts. Science, this issue p. 387 A graphene source of cold electrons lowers the subthreshold swing and supply voltage in field-effect transistors. An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS), 60 millivolts per decade, in field-effect transistors (FETs). We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS-FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current I60 of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state-of-the-art silicon 14-nanometer node FETs, a similar on-state current Ion is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off-state.