Jia Si

Carbon Nanotube Feedback-Gate Field-Effect Transistor: Suppressing Current Leakage and Increasing On/Off Ratio

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

Water-Assisted Preparation of High-Purity Semiconducting (14,4) Carbon Nanotubes

Semiconducting single-walled carbon nanotubes (s-SWNTs) with diameters of 1.0-1.5 nm (with similar bandgap to crystalline silicon) are highly desired for nanoelectronics. Up to date, the highest reported content of s-SWNTs as-grown is ∼97%, which is still far below the daunting requirements of high-end applications. Herein, we report a feasible and green pathway to use H2O vapor to modulate the structure of the intermetallic W6Co7 nanocrystals. By using the resultant W6Co7 nanocatalysts with a high percentage of (1 0 10) planes as structural templates, we realized the direct growth of s-SWNT with the purity of ∼99%, in which ∼97% is (14,4) tubes (diameter 1.29 nm). H2O can also act as an environmentally friendly and facile etchant for eliminating metallic SWNTs, and the content of s-SWNTs was further improved to 99.8% and (14,4) tubes to 98.6%. High purity s-SWNTs with even bandgap determined by their uniform structure can be used for the exquisite applications in different fields.

Large-area growth of ultra-high-density single-walled carbon nanotube arrays on sapphire surface

A scalable approach to obtaining high-density, large-area single-walled carbon nanotube (SWNT) arrays is essential for realizing the full potential of SWNTs in practical electronic devices; this is still a great challenge. Here, we report an improved synthetic method for large-area growth of ultra-high-density SWNT arrays on sapphire surfaces by combining Trojan catalysts (released from the substrate, to assure ultra-high density) with Mo nanoparticles (loaded on the surface, to stabilize the released Trojan catalysts) as cooperating catalysts. Dense and perfectly aligned SWNTs covered the entire substrate and the local density was as high as 160 tubes/μm. Field-effect transistors (FETs) built on such arrays gave an output current density of −488 μA/μm at the drain-source voltage (Vds) = the gate-source voltage (Vgs) =–2 V, corresponding to an on-conductance per width of 244 μS/μm. These results confirm the wide range of potential applications of Trojan-Mo catalysts in the structure-controlled growth of SWNTs.

High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide

High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2 V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits

A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials.

Scalable Preparation of High-Density Semiconducting Carbon Nanotube Arrays for High-Performance Field-Effect Transistors

Although chemical vapor deposition (CVD)-grown carbon nanotube (CNT) arrays are considered ideal materials for constructing high-performance field-effect transistors (FETs) and integrated circuits (ICs), a significant gap remains between the required and achieved densities and purities of CNT arrays. Here, we develop a directional shrinking transfer method to realize up to 10-fold density amplification of CNT array films without introducing detectable damage or defects. In addition, the method improves the film uniformity while retaining the perfect alignment and high carrier mobility of 1600 cm2 V-1 s-1 of CVD-grown CNT arrays. By combining the density amplification method with the thermocapillary flow method developed by Rogers et al., semiconducting CNT arrays with high densities and high qualities are obtained. High-performance FETs with a channel length of 200 nm are demonstrated using these high-density semiconducting CNT arrays, yielding a record-high on-state current density of 150 μA/μm, a peak transconductance of 80 μS/μm, and a current on/off ratio of more than 104 among the CVD-grown CNT-based FETs.

Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches

Cooler electrons for transistors The operating power of field-effect transistors is constrained in part by the minimum change in voltage needed to change the current output. This subthreshold swing (SS) limit is caused by hotter electrons from a thermal electron source leaking over the potential of the gate electrode. Qiu et al. show that graphene can act as a Dirac source that creates a narrower distribution of electron energies. When coupled to a carbon nanotube channel, the decrease in SS would allow the supply voltage to be decreased from 0.7 to 0.5 volts. Science, this issue p. 387 A graphene source of cold electrons lowers the subthreshold swing and supply voltage in field-effect transistors. An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS), 60 millivolts per decade, in field-effect transistors (FETs). We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS-FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current I60 of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state-of-the-art silicon 14-nanometer node FETs, a similar on-state current Ion is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off-state.

Aligning Solution-Derived Carbon Nanotube Film with Full Surface Coverage for High-Performance Electronics Applications

The main challenge for application of solution-derived carbon nanotubes (CNTs) in high performance field-effect transistor (FET) is how to align CNTs into an array with high density and full surface coverage. A directional shrinking transfer method is developed to realize high density aligned array based on randomly orientated CNT network film. Through transferring a solution-derived CNT network film onto a stretched retractable film followed by a shrinking process, alignment degree and density of CNT film increase with the shrinking multiple. The quadruply shrunk CNT films present well alignment, which is identified by the polarized Raman spectroscopy and electrical transport measurements. Based on the high quality and high density aligned CNT array, the fabricated FETs with channel length of 300 nm present ultrahigh performance including on-state current Ion of 290 µA µm-1 (Vds = -1.5 V and Vgs = -2 V) and peak transconductance gm of 150 µS µm-1 , which are, respectively, among the highest corresponding values in the reported CNT array FETs. High quality and high semiconducting purity CNT arrays with high density and full coverage obtained through this method promote the development of high performance CNT-based electronics.