Lian-Mao Peng

CdS quantum dots sensitized TiO2 nanotube-array photoelectrodes.

Novel CdS quantum dots (QDs) sensitized TiO2 nanotube-array photoelectrodes were investigated for their photoelectrochemical (PEC) performance. The highly ordered TiO2 nanotube arrays were synthesized by anodic oxidation and CdS QDs were deposited into the pores of the nanotube arrays by a sequential chemical bath deposition method. It is found that the CdS QDs deposited in the pores of the TiO2 nanotube arrays may significantly increase the liquid junction PEC short circuit photocurrent (from 0.22 to 7.82 mA/cm2) and cell efficiency (up to 4.15%). These results clearly demonstrate that the unique nanotube structure can facilitate the propagation and kinetic separation of photogenerated charges, suggesting potentially important applications of the inorganic QDs sensitized TiO2 nanotube-array films in solar cell applications.

Repeated growth and bubbling transfer of graphene with millimetre-size single-crystal grains using platinum

Large single-crystal graphene is highly desired and important for the applications of graphene in electronics, as grain boundaries between graphene grains markedly degrade its quality and properties. Here we report the growth of millimetre-sized hexagonal single-crystal graphene and graphene films joined from such grains on Pt by ambient-pressure chemical vapour deposition. We report a bubbling method to transfer these single graphene grains and graphene films to arbitrary substrate, which is nondestructive not only to graphene, but also to the Pt substrates. The Pt substrates can be repeatedly used for graphene growth. The graphene shows high crystal quality with the reported lowest wrinkle height of 0.8 nm and a carrier mobility of greater than 7,100 cm2 V−1 s−1 under ambient conditions. The repeatable growth of graphene with large single-crystal grains on Pt and its nondestructive transfer may enable various applications.

The structure of trititanate nanotubes

A comprehensive chemical and structural analysis is made of a new type of trititanate nanotube, which is synthesized via the reaction of TiO(2) particles with NaOH aqueous solution. It is found that the trititanate nanotubes are multi-walled scroll nanotubes with an inter-shell spacing of about 0.78 nm and an average diameter of about 9 nm. An atomic model of the nanotube is derived based on information from powder X-ray diffraction, selective-area electron diffraction, high-resolution electron microscopy and structure simulations. A model nanotube may be constructed by wrapping a (100) sheet of H(2)Ti(3)O(7) along [001] with the tube axis parallel to [010].

Y-Contacted High-Performance n-Type Single-Walled Carbon Nanotube Field-Effect Transistors: Scaling and Comparison with Sc-Contacted Devices

While it has been shown that scandium (Sc) can be used for making high-quality Ohmic contact to the conduction band of a carbon nanotube (CNT) and thus for fabricating high-performance n-type CNT field effect transistors (FETs), the cost for metal Sc is currently five times more expensive than that for gold and one thousand times more expensive than for yttrium (Y) which in many ways resembles Sc. In this Letter we show that near perfect contacts can be fabricated on single-walled CNTs (SWCNTs) using Y, and the Y-contacted CNT FETs outperform the Sc-contacted CNT FETs in many important aspects. Low-temperature measurements on Y-contacted devices reveal that linear output characteristics persist down to 4.3 K, suggesting that Y makes a perfect Ohmic contact with the conduction band of the CNT. Self-aligned top-gate devices have been fabricated, showing high performance approaching the theoretical limit of CNT-based devices. In particular a room temperature conductance of about 0.55G(0) (with G(0) = 4e(2)/h being the quantum conductance limit of the SWCNT), threshold swing of 73 mV/decade, electron mobility of 5100 cm(2)/V.s, and mean free length of up to 0.639 mum have been achieved. Gate length scaling behavior of the Y-contacted CNT FETs is also investigated, revealing a more favorable energy consumption and faster intrinsic speed scaling than that of the Si-based devices.

Self-aligned ballistic n-type single-walled carbon nanotube field-effect transistors with adjustable threshold voltage.

Near ballistic n-type single-walled carbon nanotube field-effect transistors (SWCNT FETs) have been fabricated with a novel self-aligned gate structure and a channel length of about 120 nm on a SWCNT with a diameter of 1.5 nm. The device shows excellent on- and off-state performance, including high transconductance of up to 25 microS, small subthreshold swing of 100 mV/dec, and gate delay time of 0.86 ps, suggesting that the device can potentially work at THz regime. Quantitative analysis on the electrical characteristics of a long channel device fabricated on the same SWCNT reveals that the SWCNT has a mean-free-path of 191 nm, and the electron mobility of the device reaches 4650 cm(2)/Vs. When benchmarked by the metric CV/ I vs Ion/Ioff, the n-type SWCNT FETs show significantly better off-state leakage than that of the Si-based n-type FETs with similar channel length. An important advantage of this self-aligned gate structure is that any suitable gate materials can be used, and in particular it is shown that the threshold voltage of the self-aligned n-type FETs can be adjusted by selecting gate metals with different work functions.

Growth and Performance of Yttrium Oxide as an Ideal High-κ Gate Dielectric for Carbon-Based Electronics

High-quality yttrium oxide (Y(2)O(3)) is investigated as an ideal high-kappa gate dielectric for carbon-based electronics through a simple and cheap process. Utilizing the excellent wetting behavior of yttrium on sp(2) carbon framework, ultrathin (about few nm) and uniform Y(2)O(3) layers have been directly grown on the surfaces of carbon nanotube (CNT) and graphene without using noncovalent functionalization layers or introducing large structural distortion and damage. A top-gate CNT field-effect transistor (FET) adopting 5 nm Y(2)O(3) layer as its top-gate dielectric shows excellent device characteristics, including an ideal subthreshold swing of 60 mV/decade (up to the theoretical limit of an ideal FET at room temperature). The high electrical quality Y(2)O(3) dielectric layer has also been integrated into a graphene FET as its top-gate dielectric with a capacitance of up to 1200 nF/cm(2), showing an improvement on the gate efficiency and on state transconductance of over 100 times when compared with that of its back-gate counterpart.

A high-performance top-gate graphene field-effect transistor based frequency doubler

A high-performance top-gate graphene field-effect transistor (G-FET) is fabricated, and used for constructing a high efficient frequency doubler. Taking the advantages of the high gate efficiency and low parasitic capacitance of the top-gate device geometry, the gain of the graphene frequency doubler is increased about ten times compared to that of the back-gate G-FET based device. The frequency response of the frequency doubler is also pushed from 10 kHz for a back-gate device to 200 kHz, at which most of the output power is concentrated at the doubled fundamental frequency of 400 kHz.

Quantum Capacitance Limited Vertical Scaling of Graphene Field-Effect Transistor

A high-quality Y2O3 dielectric layer has been grown directly on graphene and used to fabricated top-gate graphene field-effect transistors (FETs), and the thickness of the dielectric layer has been reduced continuously down to 3.9 nm with an equivalent oxide thickness (EOT) of 1.5 nm and excellent insulativity. By measuring CV characteristics of two graphene FETs with different gate oxide thicknesses, the oxide capacitance and quantum capacitance are retrieved directly from the experimental CV data without introducing any additional fitting process and parameters, yielding a relative dielectric constant of κ=10 for Y2O3 on graphene and an oxide capacitance of about 2.28 μF/cm2. It is found that for a rather large gate voltage range, this oxide capacitance is comparable and sometimes even larger than the quantum capacitance of graphene. Since the total gate capacitance is determined by the smaller of the oxide and quantum capacitance, our results show that not much further improvement can be gained via further vertical scaling down of the gate oxide, suggesting that Y2O3 may be the ultimate dielectric material for graphene. It is also shown that the Y2O3 gate dielectric layer with EOT of 1.5 nm may also satisfy the ultimate lateral scaling requirement on the gate length of graphene FET and be used effectively to control a graphene FET with a gate length as small as 1 nm.

CMOS-based carbon nanotube pass-transistor logic integrated circuits

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.

Scaling carbon nanotube complementary transistors to 5-nm gate lengths

Moving transistors downscale One option for extending the performance of complementary metal-oxide semiconductor (CMOS) devices based on silicon technology is to use semiconducting carbon nanotubes as the gates. Qiu et al. fabricated top-gated carbon nanotube field-effect transistors with a gate length of 5 nm. Thin graphene contacts helped maintain electrostatic control. A scaling trend study revealed that, compared with silicon CMOS devices, the nanotube-based devices operated much faster and at much lower supply voltage, and they approached the limit of one electron per switching operation. Science, this issue p. 271 Carbon nanotube field-effect transistors approach the quantum limit of one electron per switching operation. High-performance top-gated carbon nanotube field-effect transistors (CNT FETs) with a gate length of 5 nanometers can be fabricated that perform better than silicon complementary metal-oxide semiconductor (CMOS) FETs at the same scale. A scaling trend study revealed that the scaled CNT-based devices, which use graphene contacts, can operate much faster and at much lower supply voltage (0.4 versus 0.7 volts) and with much smaller subthreshold slope (typically 73 millivolts per decade). The 5-nanometer CNT FETs approached the quantum limit of FETs by using only one electron per switching operation. In addition, the contact length of the CNT CMOS devices was also scaled down to 25 nanometers, and a CMOS inverter with a total pitch size of 240 nanometers was also demonstrated.