Mahesh B. Patil

Measurement and analysis of charge injection in MOS analog switches

The analysis has been extended to the general case including signal-source resistance and capacitance. Universal plots of percentage channel charge injected are presented. Normalized variables are used to facilitate usage of the plots. The effects of gate voltage falling rate, signal-source level, substrate doping, substrate bias, switch dimensions, as well as the source and holding capacitances are included in the plots. A small-geometry switch, slow switching rate, and small source resistance can reduce the charge injection effect. On-chip test circuitry with a unity-gain operational amplifier, which reduces the disturbance imposed by measurement equipment to a minimum, is found to be an excellent monitor of the switch charge injection. The theoretical results agree with the experimental data.

Power-area evaluation of various double-gate RF mixer topologies

In this letter, we analyze the suitability of the double gate MOSFETs (DG MOSFETs) for RF-mixer applications from the point of optimizing the transconductance gain, power consumption, and area. Mixer topologies using the 0.13-/spl mu/m conventional MOSFETs, simultaneously driven DG MOSFETs (SDDG) and the independently driven DG MOSFETs (IDDG) are compared using extensive device simulations. In the frequency range 1-40 GHz, our simulation results show that the mixer circuits realized using the SDDG technologies show an order of magnitude lower power-area product, for a given transconductance gain, compared to the conventional and the IDDG technologies.

Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization

This paper presents application and effectiveness of Hierarchical particle swarm optimization (HPSO) algorithm for automatic sizing of low-power analog circuits. For the purpose of comparison, circuits are also designed using PSO and Genetic Algorithm (GA). CMOS technologies from 0.35 µm down to 0.13 µm are used. PVT (process, voltage, temperature) variations are considered during the design of circuits. We show that HPSO algorithm converges to a better solution, compared to PSO and GA. For CMOS Miller OTA, even performance of the circuit designed by HPSO algorithm is better than the performance of recently reported manually designed circuit. For the first time, design of this OTA, in 0.4 V supply voltage, is also presented. For this new design, HPSO algorithm has taken 23.5 minutes of CPU time on a Sun system with1.2 GHz processor and 8 GB RAM.

Analytical model for I-V characteristics of JFETs with heavily doped channels

Abstract A theoretical analysis of the I - V characteristics of junction field-effect transistors (JFETs) of types useful for electronic and optoelectronic integrated circuits, has been carried out in some detail. Attempts have been made to study the effects of various device parameters, including carrier degeneracy due to heavy doping of the channel, velocity overshoot of electrons in the channel and shortening of gate length, on the I - V characteristics of these JFETs. A new theoretical model for drift velocity v in semiconductors has been proposed for this purpose. A comparison of results from this model with those from the existing model of Trofimenkoff and with available experimental data for v attests at least to the high-field accuracy of the proposed model. Unlike almost all other models, the simple functional form of the proposed model provides it with additional advantages for application to the analytical I - V study of FETs with both uniformly and nonuniformly doped channels. Use of this model in the framework of the Lehovec-Zuleeg procedure for short-channel FETs appears to provide reasonably good results. Wherever experimental data are available, they agree at least qualitatively with results from the present model. The latter demonstrates that a very heavy doping in the p -type gate does not yield higher transconductance. A submicron gate and a heavy doping (higher than the nulled degeneracy level) in the channel are, on the other hand, necessary for higher drain saturation current and transconductance. A semiconductor alloy with the highest possible electron saturation velocity is the most suitable for high-speed JFETs.

On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology

A generalized methodology for modeling the effects of process variations on circuit delay performance is proposed by directly relating the variations in process parameters to variations in delay metric of a digital circuit. The 2-input nand gate is used as a library element for 65 nm gate length technology, whose delay is extensively characterized by mixed-mode simulations. This information is then used in a general-purpose circuit simulator SEQUEL, by incorporating appropriate templates for the nand gate library. A 4-bit times 4-bit Wallace tree multiplier circuit, consisting of about 300 2-input nand gates, is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized by an extensive Monte Carlo analysis. To extend this methodology for a generic technology library with a variety of library elements, modeling of nand gate delays by response surface methodology (RSM), in terms of process parameters, is carried out using design of experiments (DOE). A simple piecewise quadratic model, based on the least squares method (LSM), is proposed for one-parameter variation to address significant cubic effects observed in the delay response function. Then, a hybrid model for gate delays is generated by superimposing the interaction terms of DOE-RSM model upon the quadratic model of one-parameter variation to address the generalized case of simultaneous variations in multiple process parameters. The proposed methodology has been demonstrated for nand gate library with 266 gates, and the simplicity and generality of the approach make it equally applicable to a large library of cells for both statistical timing analysis and statistical circuit simulation at the gate level

A new approach to model nonquasi-static (NQS) effects for MOSFETs. Part II: Small-signal analysis

We present a new approach to model nonquasi-static (NQS) effects in a MOSFET in a small-signal situation. The model derived here is based on the large-signal NQS model previously proposed. The derivation of the small-signal model is presented. The small-signal parameters obtained with this model prove to be accurate up to very high frequencies. An excellent match between the new model and device simulation results has been observed even when the frequency is many times larger than the cutoff frequency.

Analysis of breakdown voltage and on resistance of super junction power MOSFET CoolMOS/sup TM/ using theory of novel voltage sustaining layer

Conventional VDMOS (vertically double diffused metal oxide semiconductor) Technology for power devices was constrained by the Silicon Limit. This is now improved to have a linear relation between on resistance (R/sub on/) and breakdown voltage (BV) instead of the quadratic relation. Theory of novel voltage sustaining layers (SJ-theory) recently published analytically models the super junction drift layers (SJ-drift layer). The authors have designed SJ-layers based on this theory and used to construct the SJ-MOSFET: CoolMOS structure. The claim of the theory that the doping level in the drift layer can now be increased by at least me order of magnitude without lowering BV is analyzed in detail. With the new silicon limit, one now can increase BV of a power device, just by increasing thickness of the SJ-drift layer. R/sub on/ and BV relationship as the thickness of the device varies is analyzed with the help of simulation. The limitations and constraints of applying SJ-theory for the CoolMOS structure are discussed. The SJ- theory does not model the behavior of R/sub on/ and BV for a fixed geometry as doping level changes. The authors observed that for a fixed geometry the rate of reduction of the BV depends on the cell pitch. This rate is large for the higher cell pitch. The effect of charge imbalance created due the channel region in CoolMOS is also investigated.

Transient simulation of semiconductor devices using the Monte-Carlo method

Abstract A technique to extract transient currents from Monte-Carlo (MC) simulation data is described. It is based on the fact that the integrated terminal current obtained from the MC data is a reasonably smooth function of time and can be easily fitted with a polynomial. The transient current is obtained by simply differentiating the polynomial. The technique is an effective way to get around the statistical noise problem that is inherent in the MC method. A MESFET structure is discussed as an example and the transient terminal currents due to a step change in the gate voltage are obtained. The current gain h 21 of the MESFET is computed from the transient currents. The technique described here can be trivially extended to other semiconductor devices and it can be a very useful tool in estimating microwave performance, large-signal behavior, switching response in logic circuits etc.

Parameter extraction for PSP MOSFET model using hierarchical particle swarm optimization

The particle swarm optimization (PSO) algorithm is applied to the problem of MOSFET parameter extraction for the first time. It is shown to perform significantly better than the genetic algorithm (GA). Several modifications of the basic PSO algorithm have been implemented: (a) Hierarchical PSO (HPSO) in which particles are hierarchically arranged and influenced by the positions of the local and global leaders, (b) memory loss operation due to which a particle forgets its past best position, (c) intensive local search in which the solution space around the global leader is searched with a high resolution, and (d) adaptive inertia which causes the inertia of the particles to change adaptively, depending on the fitness of the population. It is demonstrated that the above features improve the performance of the basic PSO algorithm both for the MOSFET parameter extraction problem and for benchmark functions.

A new public-domain simulator for power electronic circuits

A new public-domain simulator (SEQUEL) for power electronic circuits is described. The organization of the simulator is briefly discussed. The most important feature of the simulator is that the user can define new elements in a flexible manner. The differences between the new simulator and other simulators are enumerated. Some simulation examples are discussed to demonstrate the applications of the simulator. It is pointed out that the new simulator is particularly attractive for engineering institutes in developing countries where access to expensive commercial packages with similar capabilities may be difficult.