Hou-Ming Chen

A Multiphase-Output Delay-Locked Loop With a Novel Start-Controlled Phase/Frequency Detector

This paper presents a multiphase-output delay-locked loop (MODLL). The proposed phase/frequency detector (PFD) utilizes a new NAND-resettable dynamic D-flip-flop (DFF) circuit to achieve a shorter reset path. Thus, lower power consumption and higher speed can be obtained. The proposed voltage-controlled delay element used in this design can operate at a lower supply voltage and overcome the dead-band issue of the voltage-controlled delay line. An experimental multiphase-output DLL was designed and fabricated using a TSMC 0.35-mum 2P4M CMOS process. The delay-locked loop (DLL) power consumption is 3.4 mW with a 2 V supply and a 100 MHz input. The measured rms and peak-to-peak jitters are 17.575 ps and 145 ps, respectively. In addition, the supply voltage of the experimental multiphase-output DLL can vary from 1.5 V to 2.5 V without causing malfunctions. The active area is 426 mum x 381 mum.

An Exact Current-Mode PFM Boost Converter With Dynamic Stored Energy Technique

A novel pulse frequency modulation step-up dc-dc converter with maximum power conversion of 91.91% and steady-state accuracy of 0.33% is presented in this letter. The high efficiency and exact output are achieved by a dynamic stored energy technique that enhances utility rate of energy with less power consumption. This technique uses a dynamic sensing current controller and a load current detector that accurately generates different energy according to various load conditions. The boost converter has been designed and fabricated with a standard TSMC 3.3/5 V 0.35- mum 2P4M CMOS technology. Experimental results show that the output up-ripple voltage variation was 2.5 mV (6.1-8.6 mV), whereas its fixed energy counterpart was 39.4 mV (8.6-48 mV). The proposed boost converter has 16% higher power conversion efficiency than the conventional fixed energy technique at 1 mA load current.

A novel start-controlled phase/frequency detector for multiphase-output delay-locked loops

In this paper, a novel start-controlled phase/frequency detector (PFD) for multiphase-output delay-locked loops (MODLLs) is presented. In the proposed PFD, the start-controlled circuit is used to provide a precise multiphase-output without the locking problem. The PFD utilizes a new NAND-resetable dynamic DFF so that a shorter reset path is achieved. Thus, lower power consumption and higher speed can be obtained. A MODLL using the proposed start-controlled PFD is post-layout simulated using the TSMC 0.35-/spl mu/m 2P4M CMOS process. The results show that the total delay time between the input and the output of the MODLL is just one clock cycle and all of the delay cells provide precise multiphase-output without false locking or harmonic locking. Compared to the static DFF based start-controlled PFD, the power consumption of the proposed NAND-resetable dynamic DFF based PFD is reduced at least 61%. The power consumption of the proposed start-controlled PFD is 100 /spl mu/W at 2V and 100MHz. The area of the MODLL circuit is 426 /spl mu/m /spl times/ 381 /spl mu/m.

A new temperature-compensated CMOS bandgap reference circuit for portable applications

This paper presents a new temperature compensation generator (T.C.G.), which is added to a conventional bandgap reference circuit to improve the temperature drift within wider temperature range. The proposed circuit, which operates under the voltages for portable applications, for example 2.5V~5V, has good performances of the line regulation and the temperature coefficient. The proposed circuit is designed by 0.35mum CMOS technology with Vthn=0.80V and |Vthp|=1.0V. The output reference voltage obtained is 500.48plusmn0.061 mV at 27degC. A temperature coefficient of 1.4 ppm/degC from -40degC to 140degC and a line regulation of 0.17mV/V within 2.5V~5.0V supply voltage can be achieved. In addition, the proposed circuit can operate down to a 1.8-V supply

A Two-Phase Fully-Integrated DC–DC Converter With Self-Adaptive DCM Control and GIPD Passive Components

This paper presents a two-phase fully-integrated dc-dc converter for system-in-package systems with passive components fabricated using a glass-substrate-integrated passive device (GIPD) process. The proposed self-adaptive discontinuous conduction mode (DCM) controller and low-swing/full-swing buffer were incorporated to reduce the switching loss and maintain high efficiency at high switching frequency. A secondary phase and phase controller were added to increase the output power and reduce the output ripple. The proposed GIPD solution packages a standard complementary metal-oxide-semiconductor process and GIPD process in 3-D format to reduce the footprint of the system. The proposed self-adaptive DCM controller and low-swing/fullswing buffer improve efficiency of 15% in measurement compared to our previous work on the GIPD process in simulation. The peak efficiency of the proposed converter was 79.09% at a 400-mA load current, 5% higher than the peak efficiency presented in previous study. The maximal output power could reach 720 mW and the maximal switching frequency (fCCM) was designed to be 70 MHz (measured at 50 MHz) with only two 6-nH inductors and one 15-nF capacitor.

Implementation of a High-Throughput Modified Merge Sort in MIMO Detection Systems

Wireless communication technology continues to advance at a rapid pace, and researchers have made tremendous progress in extending single-input single-output (SISO) systems to multiple-input multiple-output (MIMO) systems such as IEEE 802.11n, WiMAX, and LTE. However, a MIMO system requires a detector circuit to separate received data. To reduce the number of comparators required, the method of modified merge sort is proposed, and the results are compared with those of five sorting algorithms. This modified merge sort requires approximately 56% fewer comparators than a bitonic merge sort and approximately 46% fewer comparators than an odd-even merge sort. When implemented in a TSMC 0.18-μm process, the proposed chip demonstrates a throughput of up to 1200 Mbps at an operating frequency of 150 MHz.

Low-voltage zero quiescent current PFM boost converter for portable devices

This paper presents a low-voltage zero quiescent current PFM boost converter which is designed with a standard TSMC 3.3/5V 0.35-μm CMOS technology. The proposed circuit can correctly operated at 0.9V supply voltage so that it can boost 0.9V supply to 3.6V by using a ringing oscillator, a multiplexer, a precise voltage detector and a proposed feedback scheme. Moreover, the proposed PFM boost converter circuit consumes zero quiescent current.

An exact, high-efficiency PFM DC-DC boost converter with dynamic stored energy

This paper presents an exact and high-efficiency PFM dc-dc boost converter designed with a standard TSMC 3.3/5 V 0.35-mum CMOS technology. The proposed boost converter utilizes a dynamic stored energy technique to reduce output voltage variation and raise power conversion efficiency. This result is realized using a dynamic stored energy controller and a load current detector that accurately generates different energy according to various load conditions. The output up-ripple voltage variation and steady-state accuracy was 2.6 mV (5.7 mV-8.3 mV) and 0.15% whereas its fixed energy counterpart was 11.1 mV (8.1 mV-19.2 mV) and 0.35%, respectively. The proposed circuit has 6.91% higher power-conversion efficiency than conventional fixed energy technique at a 1 mA current. The maximum power-conversion efficiency is 91.75% for 50 mA output current with a 1.5 V supply.

A Low-Voltage Integrated Current-Mode Boost Converter for Portable Power Supply

This paper presents a low-voltage integrated current-mode boost converter designed with a standard TSMC 3.3/5 V 0.35-mum CMOS technology. The proposed circuit could be operated for nickel metal hydride, fuel cell and alkaline battery-powered applications. The low-voltage and high-efficiency boost converter can successfully boost IV supply to 3.3 V due to four proposed circuit structures, including PMOS power-switch integration, zero-current detector, ring oscillator and driving buffer. The simulation results show that the power efficiency is higher than 90% for 110 mA load current at 1.5 V supply.

A Monolithic Boost Converter with an Adaptable Current-Limited PFM Scheme

In this paper, a boost converter is proposed, which adopts an adaptable current-limited PFM circuit to decrease the output voltage ripple. Unlike the conventional current-limited circuits, the proposed current-limited circuit could provide the appropriate current to the output load. This is realized by using an adaptable loading feedback circuit to automatically adjust the current-limited current according to operating conditions. The proposed circuit was designed by using TSMC 0.35mum CMOS 2P4M technology. Simulation results showed that the ripple voltage could be effectively reduced 36.7% compared with the conventional circuit at the 100mA loading current