Chi Chao Wang

Design rule optimization of regular layout for leakage reduction in nanoscale design

The effect of non-rectilinear gate (NRG) due to sub-wavelength lithograph dramatically increases the leakage current by more than 15X. To mitigate this penalty, we have developed a systematic procedure to optimize key layout parameters in regular layout with minimum area and speed overhead. As demonstrated in 65 nm technology, the optimization of regular layout achieves more than 70% reduction in leakage under NRG, with area penalty of ~10% and marginal impact on circuit speed and active power.

Modeling of layout-dependent stress effect in CMOS design

Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90 nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically captures this behavior is essential to bridge the process technology with design optimization. In this paper, starting from the first principle, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for efficient model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. They are comprehensively validated by TCAD simulation and published Si-data, including the state-of-the-art strain technologies and the STI stress effect. By embedding them into circuit analysis, the interaction between layout and circuit performance is well benchmarked at 45 nm node.

Simulation of random telegraph noise with 2-stage equivalent circuit

With the continuous reduction of CMOS device dimension, the importance of Random Telegraph Noise (RTN) keeps growing. To determine its impact on circuit performance and optimize the design, it is essential to physically model RTN effect and embed it into the standard simulation environment. In this paper, a new simulation method of time domain RTN effect is proposed to benchmark important digital circuits: (1) A two-stage L-shaped circuit is proposed to generate RTN signal by integrating a white noise source. An L-shaped circuit is a RC filter connected with an ideal comparator, where RC values are calibrated with the physical property of RTN; (2) This sub-circuit is fully compatible with SPICE, enabling the time domain analysis in nanometer scale digital design; (3) The importance of discrete RTN is demonstrated on a 32nm SRAM design and a 22nm low power ring oscillator (RO), using the proposed method. As compared to traditional 1/f noise, the impact of RTN is more significant under low voltages, leading to tremendous differences in the prediction of Vccmin and failure probability in SRAM, as well as jitter noise in RO.

Compact modeling of stress effects in scaled CMOS

Strained Si is implemented into the standard CMOS process to enhance carrier transport properties since the 90 nm technology node. However, due to the non-uniform stress distribution in the channel, the enhancement of carrier mobility and threshold voltage strongly depend on layout parameters, such as channel length (L) and source/drain diffusion length (Lsd). In this work, a compact model that physically captures these behaviors is developed for circuit simulation with strained CMOS technology.

Compact modeling of Fe-FET and implications on variation-insensitive design

Semiconductor devices with self-feedback mechanisms are considered as a promising alternative to traditional CMOS, in order to achieve faster operation and lower switching energy. Examples include IMOS and FBFET that are operated in a non-equilibrium condition to rapidly generate mobile carriers [1–2]. More recently, Fe-FET was proposed to improve the switching by integrating a ferroelectric material as gate insulator in a MOSFET structure [3–5]. Under particular circumstance, ferroelectric capacitance is effectively negative, due to the negative slope of its polarization-electrical field (P-E) curve. This property makes the ferroelectric layer a voltage amplifier to boost surface potential, achieving fast transition. In this paper: (1) A new threshold voltage model is developed to capture the feedback of negative capacitance and IV characteristics of Fe-FET; (2) It is further revealed that the impact of random dopant fluctuation (RDF) on leakage variability can be significantly suppressed in Fe-FET, by tuning the thickness of the ferroelectric layer.

The Predictive Technology Model in the Late Silicon Era and Beyond

The aggressive scaling of CMOS technology has inevitably led to vastly increased power dissipation, process variability and reliability degradation, posing tremendous challenges to robust circuit design. To continue the success of integrated circuits, advanced design research must start in parallel with or even ahead of technology development. This new paradigm requires the Predictive Technology Model (PTM) for future technology generations, including nanoscale CMOS and post-silicon devices. This paper presents a comprehensive set of predictive modeling developments. Starting from the PTM of traditional CMOS devices, it extends to CMOS alternatives at the end of the silicon roadmap, such as strained Si, high-k/metal gate, and FinFET devices. The impact of process variation and the aging effect is further captured by modeling the device parameters under the influence. Beyond the silicon roadmap, the PTM outreaches to revolutionary devices, especially carbon-based transistor and interconnect, in order to support explorative design research. Overall, these predictive device models enable early stage design exploration with increasing technology diversity, helping shed light on the opportunities and challenges in the nanoelectronics era.

Pathfinding for 22nm CMOS designs using Predictive Technology Models

Traditional IC scaling is becoming increasingly difficult at the 22nm node and beyond. Dealing with these challenges increase product development cycle time. For continued CMOS scaling, it is essential to start design explorations in new process nodes as early as possible. Such an effort requires having Predictive Technology Models, which bridge technological and design practices, in order to assess the performance impact of future key modules. In this paper we propose a strategy that enables simultaneous investigation of advanced process and design concepts. Based on a customized predictive methodology and silicon data at 90–45nm nodes, compact transistor and interconnect models are developed for the next generation CMOS technology. We capture the heuristic device behavior during the scaling, which helps us to gain key insights that allow us to make tradeoffs of circuit performance metrics for next technology node.

Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation

For nanoscale CMOS devices, gate roughness has severe impact on the device I-V characteristics, particularly in the subthreshold region. In particular, the nonrectangular gate (NRG) geometries are caused by subwavelength lithography and have relatively low spatial frequency. In this paper, we present an analytical approach to model NRG effects on I -V characteristics. To predict the change of I- V characteristics due to the NRG effect, the proposed model converts the postlithography gate profile into an equivalent gate length (Le) , which is a function of the gate bias voltage but independent of the drain bias voltage. We demonstrate the accuracy of this approach by comparing it to TCAD simulation results for 65-nm technology. The new Le model is readily integrated into standard transistor models in traditional circuit simulation tools, such as SPICE, for both dc and transient analyses. We further develop a generic procedure to systematically extract the Le value from the postlithography gate profile. The interaction with the narrow-width effect is also efficiently incorporated into the proposed algorithm. TCAD verification demonstrates that the proposed Le model is simple for implementation, scalable with both transistor geometries and bias conditions, and also continuous across all the operation regions.

Intrinsic Variability and Reliability in Nano-CMOS

Introduction It is widely recognized that process variations and reliability issues will have profound impact on nearly all aspects of future IC design. Depending on their sources, they are often categorized into two types: intrinsic fluctuations and process-induced change [1][2]. Processinduced variations are caused by the imperfection in silicon fabrication, varying from foundries to foundries. On the other side, intrinsic variability and reliability, induced by atom-level charge and geometry fluctuations, are inherent to the device structure. They are limited by fundamental physics, posing one of the ultimate barriers to continual technology scaling. Examples of intrinsic variations include random dopant fluctuation (RDF), line edge roughness (LER), oxide thickness fluctuation (OTF), and bias temperature instability (BTI) [1]-[3]. Their importance is rapidly increasing as device feature size approaches the atom dimension.

The potential of Fe-FET for robust design under variations: A compact modeling study

Semiconductor devices with self-feedback mechanisms are considered as a promising alternative to traditional CMOS, in order to achieve faster operation and lower switching energy. Examples include IMOS and FBFET that are operated in a non-equilibrium condition to rapidly generate mobile carriers. More recently, Fe-FET was proposed to improve the switching by integrating a ferroelectric material as gate insulator in a MOSFET structure. Under particular circumstance, ferroelectric capacitance is effectively negative, due to the negative slope of its polarization-electrical field (P-E) curve. This property makes the ferroelectric layer a voltage amplifier to boost surface potential, achieving fast transition. In this paper, a new threshold voltage model is developed to capture the feedback of negative capacitance and IV characteristics of Fe-FET. It is further revealed that the impact of random dopant fluctuation (RDF) on leakage variability can be significantly suppressed in Fe-FET, by tuning the thickness of the ferroelectric layer.