David Bang

Time dependent dielectric wearout (TDDW) technique for reliability of ultrathin gate oxides

The degradation of ultrathin oxides is measured and characterized by the dual voltage time dependent dielectric wearout (TDDW) technique. Compared to the conventional time-dependent dielectric breakdown (TDDB) technique, a distinct breakdown can be determined at the operating voltage I-t curve. A noisy, soft prebreakdown effect occurs for 1.8-2.7 nm ultrathin oxides at earlier stress times. The different stages of wearout of 1.8-2.7 nm oxides are discussed. The wearout of oxide is defined when the gate current reaches a critical current density at the circuit operating voltage. Devices still function after the soft breakdowns occur, but are not functional after the sharp breakdown. However, application of the E model to project the dielectric lifetime shows that this is more than 20 y for thermal oxides in the ultrathin regime down to 1.8 nm.

Performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling gate oxides

Summary form only given. In this paper, we report the performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling (DT) gate oxides. Both pure oxides and nitrided oxides down to 17 /spl Aring/ were investigated. For a L/sub g/ of about 90 nm (L/sub eff/ of about 50 nm), a drive current of larger than 1.0 mA//spl mu/m and a transconductance of higher than 800 mS/mm were obtained at room temperature. Channel electron transport properties were investigated. High field mobility degradation with decrease of oxide thickness and subsequent improvement with use of nitrided oxides were observed. Reliability characteristics such as gate leakage, stress-induced-leakage, and hot-carrier degradation are described. A new mechanical stress induced leakage phenomenon for ultra thin DT oxides was revealed.

Effect of Cu damascene metallization on gate SiO/sub 2/ plasma damage

The effect of using a Cu damascene process on plasma process-induced damage (PPID) is studied in relationship to future scaling rules. Wafers processed using a Cu damascene metallization scheme show little increase in gate leakage as antenna ratios are increased. This is in contrast to conventional Al wafers, which show a significant increase in gate leakage as the antenna ratio is increased. Applying this result to future technology generations shows that wafers produced with a Cu damascene process have the potential to exhibit significantly less gate leakage for future technology generations.