Chi-Cheng Kuo

Design of Software-Defined Radio Channel Simulator for Wireless Communications: Case Study With DSRC and UWB Channels

The software-defined radio (SDR) channel simulator is designed for testing the baseband transceiver of various wireless communication systems. The SDR architecture and the reconfiguration scheme used for changing the channel conditions and reconfiguring the hardware of the processing modules in the SDR channel simulator are presented. The simulator is capable of simulating four multipath fading channels and dedicated fading channels operating in various air interface specifications of wireless communication systems according to the demands of users. An example of the SDR channel simulator implemented with the air interface standards of dedicated short-range communications (DSRC) and ultrawideband (UWB) systems is carried out to observe the characteristics of two multipath fading channels and the hardware reconfiguration capability of processing modules and validate its correctness. The functions of the proposed SDR channel simulator can be extended to other new or modified air interface specifications of wireless communication systems without any hardware modification.

Design of a software defined radio channel simulator for mobile communications: Performance demonstration with DSRC for different vehicle speeds

The reconfiguration scheme and channel algorithms of the software defined radio (SDR) channel simulator is designed for testing the base band transceiver of various mobile radio systems. The flexibility in selecting a combination of waveform and fading channel software modules and setting the system parameters is the main feature of the SDR channel simulator. An example of the SDR channel simulator implemented with the air interface standard of the dedicated short range communications (DSRC) system for different vehicle speeds is carried out to observe its performance and validate its correctness.

Performance Improvement of the DSRC System Using a Novel S and PI-Decision Demapper

Based on the constellation diagram of the different modulations, a novel S and pi -decision rules are designed for the analog demapper of the OFDM systems. The DSRC system is chosen as an OFDM platform to compare the performance among the proposed S and pi -decision decoder, hard-decision and soft-decision decoders. Simulation results demonstrate that both the complexity and performance of S and pi -decision demapper used for M-ary QAM OFDM system can be greatly improved. The number of decisions between the received symbol and constellation points can be simplified to look up table log2 M times for M-ary QAM OFDM system.

Realization of DBF-OFDM Transceiver for Vehicular Communication Using FPGA Chip

Following the Dedicated Short Range Communications (DSRC) vehicular communications IEEE802.11p physical layer standards, this paper implements the OFDM baseband processing modules on the FPGA platform. The digital beam-forming (DBF) smart antenna technology is applied for Orthogonal Frequency Division Multiplexing (OFDM) transceiver to identify the cars on the highway and to improve the bit error rate (BER) performance in applications of DSRC vehicular communication transceivers on the vehicle position system (VPS)-based electronic toll collection (ETC) system. Three-element array antenna is chosen in order to satisfy the FPGA chips constraint of processing 108 bits data per time clock. The experimental results demonstrate that three-element DBF-OFDM is superior to SISO-OFDM about 4dB gain in signal to noise ratio (SNR). Both the DBF-OFDM and SISO-OFDM operated in 13ns delay spread fading channel have the better performance than 26ns delay spread fading channel when the BER is 10-5. The performance for both the DBF-OFDM and SISO-OFDM systems operated in 60km/h user speed is better than 120km/h user speed.

SDR structure based CFO estimation and compensation circuit for OFDM systems using reconfigurable CORDIC FPGA modules

In this paper, a software defined radio (SDR) structure based carrier frequency offset (CFO) estimation and compensation circuit is designed for an orthogonal frequency division multiplexing (OFDM) system using the reconfigurable coordinate rotation digital computer (CORDIC) field programmable gate array (FPGA) rotation and vectoring circuit modules. The SDR architecture of the CFO estimation and compensation circuit and the program flow of the CORDIC FPGA modules are presented. The required processing time and hardware reconfiguration function are our major design considerations. The experimental results demonstrate that the designed CFO estimation and compensation circuit implemented with a 10 MHz clock FPGA chip can reduce the residual CFO to an acceptable range within 1.5µsec.

Novel UWB in-vehicle channel measurement approach based on chirp pulse sounding signal

The ultra-wide band (UWB) in-vehicle channel measurement through sounding the channel with the chirp pulse signal is proposed in the paper. An UWB channel impulse response (CIR) estimator using de-convolution technique is presented to compare the measurement error of the UWB CIR generated from the chirp sounding pulse signal and the Gaussian pulse sounding signal, respectively. The noise resistance performance of the proposed UWB channel measurement approach is analyzed to verify the correctness of the measured channel data generated from the experiments.

FPGA Implementation of SDR Based CFO Estimation and Compensation Circuit for OFDM System

Based on software defined radio (SDR) architecture, this paper develops a reconfigurable CORDIC vectoring module (CVM) and CORDIC rotation module (CRM) in FPGA to implement the carrier frequency offset (CFO) estimation and compensation circuits of an orthogonal frequency division multiplexing (OFDM) system. The experimental results show that the proposed SDR-pipelined architecture can save power and hardware resource compared with conventional pipelined architecture, because the designed CVM and CRM modules can be reused in the processing modules of CFO estimation and compensation circuit. The performance trade-off for CVM and CRM implemented with different quantized float number in FPGA is presented. Furthermore, the hardware reconfiguration function of CVM and CRM is also validated.

FBFN-Based Pointing Error Correction Architecture in Wind-Force Environments

Beam pointing error caused by wind force significantly affects the performance of the wireless communications. We develop a fuzzy basis function network (FBFN) architecture to estimate the angle error of planar array antenna. The wind force model measured in Taiwan is related to the beam pointing error model for the validation of accuracy and processing time of the proposed FBFN correction architecture.

Suboptimum Channel Estimate for MIMO-OFDM System in Time-Varying Fast Fading Channels

In this paper, an adaptive path number selection mechanism is proposed to improve the accuracy of the frequency channel response obtained from the pilot- based channel estimation approach for QAM modulated MIMO-OFDM systems. The 2×2 space-frequency block code-dedicated short-range communication (2×2 SFBC- DSRC) system and a six-path channel model are considered as an example of the MIMO-OFDM system in the simulations. Simulation results prove the relevant benefits of the proposed suboptimum channel estimation approach used in time-varying fast fading channels.

The cognitive null control engine for next generation wireless networks

This article has provided an intelligent interference cancellation (IC) technique in spatial domain that can be employed in the future cognitive wireless network. The cognitive null control engine is proposed to control the number of nulls of software defined radio (SDR) digital beamformer (DBF) in order to maintain the receiver bit error rate (BER) below 10-5 over the changing interference and angular spread environments. Due to complexity consideration, the cognitive null control engine is considered to be implemented in the base station receiver of next generation wireless networks.