Jeich Mar

An ANFIS controller for the car-following collision prevention system

This paper presents a controller based on an adaptive network fuzzy inference system (ANFIS) for the car-following collision prevention system to nonlinearly control the speed of the vehicle. The distance and speed relative to the car in front are measured by a radar sensor and applied to the controller. The output acceleration or deceleration rate of the controller is based on the characteristics of the vehicles. The initial input and output membership functions and 25 rules of ANFIS are constructed by a fuzzy inference system (FIS). The design method of the reference signals, which is used to update on-line the consequent parameters of ANFIS according to recursive least square (RLS) algorithm, are proposed. The presented ANFIS controller can solve the problems of the oscillations for final distance between the leading vehicle (LV) and the following vehicle (FV) and relative speed. The required processing time to achieve safe distance between the LV and the FV is about 7-8 s, which is faster than the other models. The ANFIS controller of the car-following collision prevention system proposed in this paper can provide a safe, reasonable, and comfortable drive.

The car-following and lane-changing collision prevention system based on the cascaded fuzzy inference system

A new design for the collision prevention system based on cascaded fuzzy inference system (CFIS) for lane-changing maneuver and car-following is proposed. The lane-changing is combined with car-following to save the processing time of the lane-changing maneuver. The distance and speed relative to the vehicle in front or in target adjacent lane are measured by the spread spectrum radars and applied to the collision prevention system. The output acceleration or deceleration rate obtained from the CFIS collision prevention system is based on the characteristics of the vehicles. Monte Carlo simulations were conducted to demonstrate that the CFIS collision prevention system could provide a safe, reasonable, and comfortable drive for car-following and lane-changing. The system characteristics for car-following, lane-changing, and emergency braking are verified.

A car-following collision prevention control device based on the cascaded fuzzy inference system

A car-following collision prevention control device based on the cascaded fuzzy inference system (CFIS), consisting of a velocity fuzzy controller and an acceleration fuzzy controller, to nonlinearly control car acceleration or deceleration rate is proposed. The distance and speed relative to the car in front are measured using spread spectrum radar and applied to the collision prevention control device. The output acceleration or deceleration rate obtained from the CFIS car-following collision prevention system is based on the characteristics of the vehicle. The simulation results demonstrate that the presented CFIS control device can solve the oscillation problems for final relative distance between the lead vehicle (LV) and following vehicle (FV) and relative speed. When the LV applies the brake suddenly or a stationary obstacle appears in front of vehicle moving at high speed on the roadway, the CFIS control device can safely avoid a collision. The CFIS car-following collision prevention control device proposed in this paper can provide a safe, reasonable and comfortable drive.

Performance analysis of cellular CDMA networks over frequency-selective fading channel

An effect of multipath fading on the performance of a cellular code-division multiple-access (CDMA) system is analyzed in this paper. A wide-sense stationary uncorrelated scattering (WSSUS) channel model and the coherent binary phase-shift keying (BPSK) with asynchronous direct-sequence (DS) spreading signal are assumed in the analysis. The average error probability for both the forward link and reverse link of a cellular CDMA system over a frequency-selective fading channel using a conventional correlation-type receiver and RAKE receiver are derived. The impact of imperfect power control and channel capacity of a cellular CDMA system is also investigated. The closed forms of average error probability derived in the paper can save a lot of computation time to analyze the performance and channel capacity of a cellular CDMA system. The analytical results show that the performance and maximum transmission rate of cellular CDMA systems degrade with an increase in the number of simultaneous users and the number of interfering cells. The signal-to-interface ratio (SIR) for the reverse link derived in this paper can directly describe the interrelationships among a number of paths, number of users, number of interfering cells, fading factors, and maximum variation of a received unfaded signal.

Design of Software-Defined Radio Channel Simulator for Wireless Communications: Case Study With DSRC and UWB Channels

The software-defined radio (SDR) channel simulator is designed for testing the baseband transceiver of various wireless communication systems. The SDR architecture and the reconfiguration scheme used for changing the channel conditions and reconfiguring the hardware of the processing modules in the SDR channel simulator are presented. The simulator is capable of simulating four multipath fading channels and dedicated fading channels operating in various air interface specifications of wireless communication systems according to the demands of users. An example of the SDR channel simulator implemented with the air interface standards of dedicated short-range communications (DSRC) and ultrawideband (UWB) systems is carried out to observe the characteristics of two multipath fading channels and the hardware reconfiguration capability of processing modules and validate its correctness. The functions of the proposed SDR channel simulator can be extended to other new or modified air interface specifications of wireless communication systems without any hardware modification.

An ANFIS-IDS against deauthentication DOS attacks for a WLAN

In this paper, an intrusion detection system (IDS) based on adaptive neuro-fuzzy inference system (ANFIS) rule is realized to minimize the detection delay for the deauthentication denial-of-service (DOS) attacks on the medium access control (MAC) layer of a wireless local area network (WLAN). Both the average sequence number gap (SNG) between the successive packets and the average statistical value of the de-authentication packets received by an Access Point (AP) are used to detect the deauthentication DoS attack. The proposed ANFIS-IDS experimental platform is implemented and tested against real deauthentication DoS attack to empirically evaluate its average detection delay (ADD) and average false alert rate (FAR). The performance of the IDS using the proposed ANFIS method is compared with non-parametric sequential change point detection (NPSCPD) algorithm in a practical WLAN environment.

Implementation of SDR Digital Beamformer for Microsatellite SAR

The hardware reconfiguration feature of a software-defined radio (SDR) architecture can support multiple modes of a digital beamformer (DBF) striving for compactness and efficient processing power, which are important issues for microsatellite synthetic aperture radar (SAR) systems. In this letter, based on the SDR architecture, a DBF system, consisting of multiple beam, direction-of-arrival (DOA) estimation, and null-steering operation modes, is realized using a field-programmable gate array (FPGA) processor. Since the hardware reconfiguration has to be processed with minimal delay, the FPGA hardware must be of modularized design. Different modes can share the common module during mode switching. Experimental results verify the performance of DOA, null steering, and mode switching. The processing time of each DBF mode is less than the cross-range pulse repetition interval of the microsatellite SAR system.

The effect of the MS speed on the traffic performance of an integrated mobile WiMAX and DSRC multimedia networks on the highway

The effect of the mobile station (MS) speed on the traffic performance of an integrated Mobile WiMAX and DSRC multimedia networks applied to the highway communication link of the vehicle position system (VPS) is presented. The probability density function (pdf) and cumulative distribution function (cdf) of cell residence time for both the new call and handoff call are derived to support the simulations in which the minimum MS speed may not be zero.

Cell planning and channel throughput of mobile WiMAX AT 2.5 GHz

Abstract A combination of COST‐231 Hata and SUI Erceg models is presented to predict the propagation path loss of 2.5 GHz Mobile WiMAX in urban, suburban, flat‐terrain with light tree (rural A), flat‐terrain with heavy tree (rural B) and hilly‐terrain rural (rural C) environments. The cell sizes for five different terrain areas, three antenna modes and 90% service reliability are estimated through the downlink link budget analysis. Based on the radio coverage calculation results, the call holding time in a given cell and channel throughput of the Mobile WiMAX are simulated to observe the relationship among mobile speed, antenna mode, operation environment and channel throughput. The effect of user mobility on the handoff rate is considered in the simulations. An example of cell planning for 2.5 GHz Mobile WiMAX is carried out for a zone near Taipei city.

Realization of OFDM Modulator and Demodulator for DSRC Vehicular Communication System Using FPGA Chip

Following the DSRC vehicular communications IEEE802.11p physical layer standards, this paper presents the required computing time estimations of baseband processing modules on the DSP platform and uses this estimation to explain the decision of choosing to implement the 64 point IFFT/FFT module with the FPGA chip. The IFFT/FFT processing time of OFDM modulator/demodulator circuits in applications of DSRC vehicular communication system transceivers must be less than the symbol interval of 8 musec in order to satisfy the requirement of real-time DSRC communications. The 64-IFFT/FFT processing module presented in this paper uses a parallel processing structure of four butterfly circuit units, is capable of processing 16-bit digital signals, and completes 64-IFFT/FFT calculations in 5.33 musec (< 8 musec) with a 24 MHz FPGA chip. Ten short training symbols of the DSRC system are sent through the FPGA IFFT/FFT module to verify its functionality and performance