You-Rong Lin

Design of Software-Defined Radio Channel Simulator for Wireless Communications: Case Study With DSRC and UWB Channels

The software-defined radio (SDR) channel simulator is designed for testing the baseband transceiver of various wireless communication systems. The SDR architecture and the reconfiguration scheme used for changing the channel conditions and reconfiguring the hardware of the processing modules in the SDR channel simulator are presented. The simulator is capable of simulating four multipath fading channels and dedicated fading channels operating in various air interface specifications of wireless communication systems according to the demands of users. An example of the SDR channel simulator implemented with the air interface standards of dedicated short-range communications (DSRC) and ultrawideband (UWB) systems is carried out to observe the characteristics of two multipath fading channels and the hardware reconfiguration capability of processing modules and validate its correctness. The functions of the proposed SDR channel simulator can be extended to other new or modified air interface specifications of wireless communication systems without any hardware modification.

Implementation of SDR Digital Beamformer for Microsatellite SAR

The hardware reconfiguration feature of a software-defined radio (SDR) architecture can support multiple modes of a digital beamformer (DBF) striving for compactness and efficient processing power, which are important issues for microsatellite synthetic aperture radar (SAR) systems. In this letter, based on the SDR architecture, a DBF system, consisting of multiple beam, direction-of-arrival (DOA) estimation, and null-steering operation modes, is realized using a field-programmable gate array (FPGA) processor. Since the hardware reconfiguration has to be processed with minimal delay, the FPGA hardware must be of modularized design. Different modes can share the common module during mode switching. Experimental results verify the performance of DOA, null steering, and mode switching. The processing time of each DBF mode is less than the cross-range pulse repetition interval of the microsatellite SAR system.

The effect of the MS speed on the traffic performance of an integrated mobile WiMAX and DSRC multimedia networks on the highway

The effect of the mobile station (MS) speed on the traffic performance of an integrated Mobile WiMAX and DSRC multimedia networks applied to the highway communication link of the vehicle position system (VPS) is presented. The probability density function (pdf) and cumulative distribution function (cdf) of cell residence time for both the new call and handoff call are derived to support the simulations in which the minimum MS speed may not be zero.

Realization of subspace-based digital beamformer using CORDIC algorithm based on software defined radio architecture

The reconfigurable multi-function matrix operation (MFMO) module circuits including eigen-value and eigen-vector decomposition (EVD), QR factorization (QRF), linear system solver (LLS), and matrix multiplier (MM) for the software defined radio and cognitive applications are designed using coordinate rotations digital computer (CORIDC) algorithm. The processing time for each scalable N×N MFMO module circuit implemented on the field programmable gate array (FPGA) is formulated. A unitary-ESPRIT (Estimating Signal Parameter via Rotational Invariance Techniques) subspace digital beamformer realized with a set of software-driven MFMO module circuits is used as an example to demonstrate the hardware reconfiguration capability. Based on the requirements of the processing time and the logic resource of the subspace digital beamformer, the proposed MFMO module circuits can be reconfigured via the reconfiguration controller (RC).

Design of a software defined radio channel simulator for mobile communications: Performance demonstration with DSRC for different vehicle speeds

The reconfiguration scheme and channel algorithms of the software defined radio (SDR) channel simulator is designed for testing the base band transceiver of various mobile radio systems. The flexibility in selecting a combination of waveform and fading channel software modules and setting the system parameters is the main feature of the SDR channel simulator. An example of the SDR channel simulator implemented with the air interface standard of the dedicated short range communications (DSRC) system for different vehicle speeds is carried out to observe its performance and validate its correctness.

SDR Based Multi-Mode DBF for micro-satellite SAR

The reconfigurable feature of software defined radio (SDR) architecture gives rise to reusability, scalability, and power efficiency. Reusability of hardware supporting multiple modes of DBF strives for compactness and efficient processing power, which are important issue for micro-satellite synthetic aperture radar (SAR) systems. In this paper, according to the SDR architecture, a digital beamforming (DBF) system comprising multiple-beams, DOA estimation and null steering beam modes is realized using an FPGA for the micro-satellite SAR system. Since the hardware reconfiguration has to be processed with minimal delay, the FPGA hardware must be of modularized design. Different modes can share the common module during mode switching.

Implementation of the SDR beamformer system on a digital signal processor

A 16-beam with equal beamwidth software defined radio (SDR) beamformer system is realized on a digital signal processor (DSP). The SDR beamformer system consists of digital multi-beam (DMB), direction of arrival (DOA), and antenna nulling modes. The general formulas for the beam patterns of the auxiliary array antenna with equal beamwidth are derived. An antenna nulling mode with an adjacent auxiliary array antenna is used as an example to compute the weight coefficient and to demonstrate the characteristics of nulling pattern.

Software defined radio channel simulator for wireless communications: Demonstrations of the hardware reconfiguration using DSRC and UWB channels

The software defined radio (SDR) channel simulator is designed and implemented in the FPGA for various wireless communication systems. The dedicated short range communications (DSRC) and ultra-wideband (UWB) channels are carried out to observe the characteristics of multi-path fading channels and validate the correctness of the SDR channel simulator. The hardware reconfiguration of the fading channel weighting generator circuit module is also demonstrated during mode switching.

A New Five-Bit 128-Tone Sigma-Delta Modulation D/A and A/D Converters for UWB-OFDM Transceiver

For the purpose of reducing the quantization noise and power consumption of UWB-OFDM transceiver, a new time domain-based interpolator and decimator structure is proposed to realize five-bit D/A and A/D converters in the five-bit 128-tone sigma-delta modulation (SDM) UWB-OFDM transceiver. The five-bit 128-tone SDM UWB-OFDM transceiver using time domain-based interpolator and decimator in place of time spreader and de-spreader can obtain time-domain spread spectrum processing gain and reduce quantization noise simultaneously. The structure of the five-bit 128-tone SDM A/D converter, which employs 32 parallel analog SDM circuits without up-sampling, is designed. Simulation results demonstrate that BER of the proposed five-bit 128-tone SDM D/A and A/D converters based on time domain-based interpolator and decimator scheme can satisfy the performance requirements of the five-bit 128-tone SDM UWB-OFDM transceiver for the QPSK, 16-QAM and 64-QAM modulations.

The time domain-based interpolation and decimation processing for N-tone sigma-delta circuit in UWB-OFDM transceiver

A new null quantization noise canceling structure designed with the time domain-based interpolation and decimation for the N-tone sigma-delta modulation (SDM) UWB- OFDM transceiver is proposed. The required length of IFFT and FFT processing will not change with the interpolation factor. The bit error rate (BER) for QPSK, 16-QAM and 64-QAM UWB- OFDM transceiver using the 128-tone SDM circuit with the optimum quantization size and additive white Gaussian noise (AWGN) channel are simulated. The null quantization noise floor generated from the 128-tone SDM circuit can be avoided when the proper interpolation factor is chosen. The proposed null quantization noise cancellation structure can greatly reduce the hardware gate count and processing time of the N-tone SDM UWB-OFDM transceiver.