Chi-Hsien Lin

Design and Analysis of a DC–43.5-GHz Fully Integrated Distributed Amplifier Using GaAs HEMT–HBT Cascode Gain Stage

Design and analysis of a dc-43.5-GHz fully integrated distributed amplifier (DA) using a GaAs high electron-mobility transistor (HEMT) heterojunction bipolar transistor (HBT) cascode gain stage is presented in this paper. The proposed DA is fabricated in a stacked 2-μm InGaP/GaAs HBT, 0.5-μm AlGaAs/GaAs enhancement- and depletion-mode HEMT monolithic microwave integrated circuit technology. A modified m -derived network and an HEMT-HBT cascode amplifier with inductive peaking technique are investigated to enhance the bandwidth of the DA. The bias networks of the DA are fully integrated in a single chip without off-chip bias-T or bias components. The measured average small-signal gain is 8.5 dB. The measured minimum noise figure is 4.2 dB. The measured maximum output 1-dB compression point (P1 dB) and the maximum output third-order intercept point are 8 and 18 dBm, respectively. Moreover, the DA is successfully evaluated with an eye diagram measurement, and demonstrates good transmission quality.

A High Efficiency Broadband Class-E Power Amplifier Using a Reactance Compensation Technique

This letter presents a high efficiency broadband fully integrated class-E power amplifier (PA) using a 0.5 μm enhancement/depletion-pseudomorphic high-electron mobility transistor (E/D-PHEMT) process. The proposed PA is based on a class-E topology with a reactance compensation technique. To achieve high efficiency and broad bandwidth, the reactance compensation component is employed in the load network of the class-E PA. From 1.5 to 3.8 GHz, this circuit demonstrates a power added efficiency (PAE) of 62% and an output 1 dB compression point (P1 dB) of higher than 27 dBm.

Q-band low noise amplifiers using a 0.15μm MHEMT process for broadband communication and radio astronomy applications

Two Q-band low noise amplifiers using a 0.15-μm InGaAs MHEMT process for broadband communication and radio astronomy applications are presented in this paper. Between 37 and 53 GHz, the LNA1 features a small signal gain of higher than 31 dB, a noise figure of better than 3.5 dB with a minimum noise figure of 2.8 dB at 44 GHz, and a gain-bandwidth product (GBP) of 679 GHz. Between 32 and 50 GHz, the LNA2 features a small signal gain of higher than 28 dB, a noise figure of better than 3.2 dB with a minimum noise figure of 2.6 dB at 44 GHz, and a GBP of 569 GHz. The chip sizes of the LNA1 and LNA2 are both 2 x 1 mm2. The LNAs demonstrate broad bandwidth, high gain, low noise figure, and compact chip size, and they will be further applied to a few broadband receivers for communications and radio astronomy applications. Moreover, this work demonstrates the highest GBP among all the reported Q-band LNAs.

A Broadband Injection-Locking Class-E Power Amplifier

This paper presents a fully integrated two-stage injection-locking class-E power amplifier (PA) using a GaAs 0.5-μm enhancement- and depletion-mode pseudomorphic high-electron mobility transistor (E/D-mode PHEMT) process. The injection-locking concept is used in this design, and the PA works as an oscillator whose output voltage is tuned at the input frequency. The proposed PA achieves high power-added efficiency (PAE) and high power gain. An autonomous circuit is also employed for the stability analysis, and the design procedure is summarized for the circuit implementation. By employing this design technique, the proposed injection-locking class-E PA under continuous-wave signal achieves a peak PAE of 59% at an output power of 26.6 dBm from a 6-V dc supply voltage. With a Gaussian minimum-shift keying (GMSK) modulation input signal at 3.5 GHz, the measured maximum PAE is 57% at an output power of 26.7 dBm. The measured error vector magnitude is within 2.2% over all of the output power level, and the adjacent channel power ratio is better than - 40 dBc. Under a 64-QAM modulation signal with class-AB operation, the proposed PA achieves a peak PAE of 55% with an output power of 27 dBm.

A Low-Phase-Noise CMOS Quadrature Voltage-Controlled Oscillator Using a Self-Injection-Coupled Technique

A modified coupled method for multiphase oscillator is proposed and demonstrated in a standard 0.18-μm CMOS technology. A self-injection-coupled (SIC) technique is used to couple two current-reused differential voltage-controlled oscillators (VCOs). Compared with the conventional parallel-coupled quadrature VCO (QVCO), the proposed QVCO using the SIC technique presents low phase noise without increasing dc power consumption. The proposed SIC-QVCO at 16.28 GHz demonstrated a low phase noise of -125 dBc/Hz at 1-MHz offset frequency and a tuning range of 290 MHz. The dc supply voltage and current consumption are 1.8 V and 6 mA, respectively. The chip size of the proposed SIC-QVCO is 0.75 × 0.6 mm2.

A 60-GHz low DC power self-injection coupling CMOS quadrature voltage-controlled oscillator with high quadrature accuracy

A 60-GHz high quadrature accuracy low dc power quadrature voltage-controlled oscillator (QVCO) using self-injection coupling (SIC) is proposed and demonstrated in 90 nm CMOS technology. By using SIC technique, this QVCO achieves low phase noise and good quadrature accuracy. Moreover, the amplitude/phase errors of the QVCO are fully characterized via a four-port vector network analyzer. The proposed 60-GHz QVCO exhibits a phase noise of -95 dBc/Hz at 1-MHz offset frequency, an amplitude error of 0.12 dB, and a phase errors of 1.2°. The dc power consumption is 13.3 mW with a supply voltage of 0.7 V. The chip size of the proposed QVCO is 0.75×0.6 mm2. This work has the lowest dc power consumption and the best figure-of-merits with high quadrature accuracy among the all reported millimeter-wave CMOS QVCOs.

24-GHz MMIC development using 0.15-µm GaAs PHEMT process for automotive radar applications

This paper presents 24-GHz monolithic microwave integrated circuit (MMIC) development for automotive radar applications. The chipset consists of a low noise amplifier (LNA), a power amplifier (PA) and a mixer. The LNA exhibits a small signal gain of 20 dB from 19 to 32 GHz with a noise figure of 3 dB. The PA achieves a small signal gain of 20 dB from 19 to 26 GHz with an output P1dB of higher than 21 dBm. The mixer exhibits a conversion loss of 9 dB from 20 to 32 GHz with a port-to-port isolation of better than 24 dB.

A

This letter presents design of a K-band high power high efficiency monolithic GaAs power oscillators using class-E load network with finite dc-feed inductance. To further extend the operation frequency up to millimeter-wave band with high efficiency, the core transistor is operated in the saturated region with overdriven condition to obtain the bifurcated current waveform. The proposed power oscillator is fabricated using a 0.15-μm GaAs pseudomorphic high-electron mobility transistor process, and it features a tuning range from 23.5 to 24.5 GHz, a peak efficiency of 19%, a maximum output power of 21 dBm, and a phase noise of -106.3 dBc/Hz at 1-MHz offset.

K

This letter presents a 2.5 GHz high efficiency high power low phase noise monolithic microwave power oscillator using 0.5- μm GaAs enhancement- and depletion-mode pseudomorphic high-electron mobility transistor process. The class-E load network with finite dc-feed inductance is adopted in the power oscillators to achieve high efficiency. The shunt capacitance and load resistance of the class-E network can be larger than those of the class-E load network with the large dc-feed inductance. With a dc supply voltage of 4 V, the proposed power oscillator demonstrates a peak efficiency of 53%, a maximum output power of 24.8 dBm, and a minimum phase noise of -127 dBc/Hz at 1 MHz offset frequency.

-Band High Efficiency High Power Monolithic GaAs Power Oscillator Using Class-E Network

This paper describes a fully integrated eightphase voltage controlled oscillator (VCO) monolithic microwave integrated circuit (MMIC) with reflection-type modulators in 0.18-μm CMOS Technology. The characterization of the amplitude and phase errors is successfully demonstrated using the proposed innovative method. The eight-phase VCO achieves a low phase noise of −117.1 dBc/Hz at 1-MHz offset frequency. For the characterization of the amplitude and phase errors, this circuit features a sideband suppression of better than −26 dBc and a LO suppression of better than −18 dBc. From the sideband suppression contours, the measured amplitude and phase errors of the eight-phase VCO are within 0.85 dB and 5°, respectively. To the best of the authors’ knowledge, this work is the first attempt to demonstrate the characterization of the amplitude and phase errors for the eight-phase VCO.