Yen-Liang Yeh

A W-Band Wide Locking Range and Low DC Power Injection-Locked Frequency Tripler Using Transformer Coupled Technique

A W-band wide locking range injection-locked frequency tripler (ILFT) with low dc power consumption is presented in this paper. By using a transformer coupled (TC) topology, the proposed TC-ILFT features the following advantages: 1) the negative resistance of the cross-coupled pair is not degraded due to the proposed TC-ILFT without source degeneration, and the TC-ILFT can be operated in lower dc supply voltage as compared to the conventional ILFTs; 2) the dc bias of the injector can be properly designed for maximizing locking range; 3) the parasitic capacitance provided by the injector can be reduced due to the impedance transformation; and 4) the larger device size of the injector can be chosen enhancing the third harmonic. Moreover, the operation frequency and the locking range of this work are boosted using a multiorder resonator. A theoretical model of the proposed TC-ILFT is also established and it has been carefully verified with the experimental results. The free-running oscillation frequency of the proposed TC-ILFT is 94.51 GHz. As the input power is -1 dBm, the measured locking range is 5.9 GHz without varactor tunning. The dc supply voltage and the power consumption are 0.7 V and 1 mW, respectively.

Design and Analysis of a

In this paper, we present design and analysis of a W-band divide-by-three injection-locked frequency divider (ILFD) in 90 nm CMOS process. Based on the proposed topology, the locking range can be enhanced without additional dc power consumption due to the boost of the second harmonic in the ILFD, and the small input capacitance is more feasible for W -Band PLL integration. The locking range of the ILFD is investigated to obtain a theoretical model. From the analysis, the locking range is proportional to the device size of the injectors and the amplitude of the injection signal. In addition, the locking range can be enhanced with a proper gate dc bias of the injectors. The measured locking range of the proposed ILFD is from 91.4 to 93.5 GHz without varactor tuning, and the output power is higher than -15 dBm. The core dc power consumption is 1.5 mW with a supply voltage of 0.7 V.

W

In this paper, we present design and analysis of an innovative low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked phase-locked loop (PLL) with self-aligned delay-locked loop in 65-nm CMOS technology. With the proposed innovative topology, the phase between the injection signal and the voltage-controlled oscillator in the PLL can be dynamically aligned to minimize the jitter over the variations. A modified theoretical model of the sub-harmonically injection-locked PLL with self-aligned injection is developed for the design methodology. The in-band phase noise of the sub-harmonically injection-locked PLL can be significantly improved using the self-aligned sub-harmonically injection-locked technique. The design considerations of the locking range, loop bandwidth, and frequency division ratio are addressed. At 10 GHz, the measured phase noise of the proposed PLL with self-aligned injection at 1-MHz offset is -130.2 dBc/Hz with a root-mean-square jitter of 44 fs. The total dc power consumption is 62.7 mW. From 10 °C to 70 °C, the measured phase noise at 1-MHz offset and jitter are better than -129 dBc/Hz and 48 fs, respectively. This work demonstrates excellent performance and good robustness over the variations, and it can be compared to the previously reported state-of-the-art sub-harmonically injection-locked PLLs.

-band Divide-by-Three Injection-Locked Frequency Divider Using Second Harmonic Enhancement Technique

A Ka-band monolithic high-efficiency frequency quadrupler using a GaAs heterojunction bipolar transistor and pseudomorphic high electron-mobility transistor technology is presented in this paper. The frequency quadrupler is constructed cascading two frequency doublers. The frequency doubler employs a modified common-base/common-source topology to enhance the second harmonic efficiently. The dc bias condition, harmonic output power, conversion gain, and efficiency for variable configurations are investigated. Two phase-shifter networks are used to reduce phase error and improve the fundamental rejection. Between 23-30 GHz, the proposed frequency quadrupler features a conversion gain of higher than -1 dB with an input power of 4 dBm. The maximum conversion gain is 2.7 dB at 28 GHz with an efficiency of up to 8% and a power-added efficiency of 3.6%. The maximum output 1-dB compression point (P1 dB) and the saturation output power (Psat) are higher than 7 and 8.2 dBm, respectively. The overall chip size is 2×1 mm2.

A Low-Jitter Low-Phase-Noise 10-GHz Sub-Harmonically Injection-Locked PLL With Self-Aligned DLL in 65-nm CMOS Technology

A 20.7% locking range W-band fully integrated injection-locked oscillator (ILO) using 90 nm CMOS technology is presented in this paper. The proposed ILO is designed using a ring-based triple-push topology. The free-running oscillation frequency of the ILO is 97.6 GHz. When the input subharmonic number is 3, the ILO demonstrates a locking range from 88.1 to 108.5 GHz without bias tuning, a minimum conversion loss of 14.6 dB, and an output power flatness of within 2 dB. When the input subharmonic number is 6, the locking range is from 96.1 to 98.4 GHz and the minimum conversion loss is 17.2 dB. The dc power consumption is 55.4 mW from 1.2-V dc supply voltage. The chip size is 0.733 × 0.492 mm2. As compared to the previously reported ILOs in the MMW band, our proposed ILO has the widest locking range and good power flatness.

Design and Analysis of a

Design and analysis of low-phase-noise low-jitter subharmonically injection-locked voltage-controlled oscillator (VCO) with frequency-locked loop (FLL) self-alignment technique is presented in this paper using 90-nm CMOS process. The issue of the narrow locking range for the subharmonically injection-locked VCO (SILVCO) can be resolved over the variations, especially for high subharmonic number and millimeter-wave band, since the control voltage is adaptively adjusted using the proposed innovative method to refer to the subharmonic input frequency. A theoretical model of the SILVCO with FLL self-alignment technique is addressed for the design consideration and phase noise evaluation. With a subharmonic number of 16, the operation frequency of the proposed K -band circuit is from 24 to 26.1 GHz. The measured minimum phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz are -114.3 dBc/Hz and 56.6 fs, respectively. As the temperature is from 20 °C to 70 °C, the measured deviations of output power, phase noise, and jitter are within 2 dB, 3 dB, and 67 fs, respectively. This paper demonstrates excellent performance and good robustness, and it can be compared with the previously reported state-of-the-art clock generators in silicon-based technologies.

Ka

A 60-GHz high quadrature accuracy low dc power quadrature voltage-controlled oscillator (QVCO) using self-injection coupling (SIC) is proposed and demonstrated in 90 nm CMOS technology. By using SIC technique, this QVCO achieves low phase noise and good quadrature accuracy. Moreover, the amplitude/phase errors of the QVCO are fully characterized via a four-port vector network analyzer. The proposed 60-GHz QVCO exhibits a phase noise of -95 dBc/Hz at 1-MHz offset frequency, an amplitude error of 0.12 dB, and a phase errors of 1.2°. The dc power consumption is 13.3 mW with a supply voltage of 0.7 V. The chip size of the proposed QVCO is 0.75×0.6 mm2. This work has the lowest dc power consumption and the best figure-of-merits with high quadrature accuracy among the all reported millimeter-wave CMOS QVCOs.

-Band Monolithic High-Efficiency Frequency Quadrupler Using GaAs HBT–HEMT Common-Base/Common-Source Balanced Topology

This paper presents linearity enhancement of CMOS device for microwave amplifier applications. The proposed method is based on a modified third-order transconductance (gm3) cancellation technique and the device is fabricated in a 0.13 µm CMOS process. For the NMOS device with the proposed gm3 cancellation technique, the third-order intermodulation distortion (IMD3) is improved by 15 dB as compared to the conventional single device. Two Ka-band CMOS amplifiers with and without the linearization are successfully evaluated. With the linearization, the measured IMD3 is enhanced by 14 dB, and the adjacent channel power ratio (ACPR) of the amplifier is improved by 7 dB for a 64-QAM modulation signal. Moreover, the linearization scheme is easily applied to the microwave amplifier and mixer designs without extra dc power consumption.

A 20.7% locking range W-band fully integrated injection-locked oscillator using 90 nm CMOS technology

In this paper, we present design and analysis of a K-band (18 to 26.5 GHz) low-phase-noise phase-locked loop (PLL) with the subharmonically injection-locked (SIL) technique. The phase noise of the PLL with subharmonic injection is investigated, and a modified phase noise model of the PLL with SIL technique is proposed. The theoretical calculations agree with the experimental results. Moreover, the phase noise of the PLL can be improved with the subharmonic injection. To achieve K-band operation with low dc power consumption, a divide-by-3 injection-locked frequency divider (ILFD) is used as a frequency prescaler. The measured phase noise of the PLL without injection is -110 dBc/Hz at 1 MHz offset at the operation frequency of 23.08 GHz. With the subharmonic injection, the measured phase noises at 1 MHz offset are -127, -127, and -119 dBc/Hz for the subharmonic injection number NINJ = 2, 3, and 4, respectively. Moreover, the performance of the proposed PLL with and without SIL technique can be compared with the reported advanced CMOS PLLs.

Design and Analysis of CMOS Low-Phase-Noise Low-Jitter Subharmonically Injection-Locked VCO With FLL Self-Alignment Technique

A Ka-band broadband frequency doubler in a 0.18 µm SiGe BiCMOS technology is presented in this paper. The frequency doubler employs a configuration of a common-base (CB)/ common-emitter (CE) pair to enhance the second harmonic efficiently. This frequency doubler features a conversion gain of higher than ™7 dB with an input power of 5 dBm between 26 and 40 GHz. The maximum output 1-dB compression point (P1dB) is 4.3 dBm and the output saturation power (Psat) is higher than 5 dBm at 31 GHz. The overall chip size is 0.85×0.66 mm2. To the best of the authors knowledge, this work demonstrates the first SiGe-based frequency doubler using CB-CE configuration with good output power and good figure-of-merit (FOM) covering the entire Ka band.