Chi-wook Kim

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Demand for higher bandwidth DRAM continues to increase, especially in high-performance computing and graphics applications. However, conventional DRAM devices such as DDR4 DIMM and GDDR5 cannot satisfy these needs since they are bandwidth limited to less than 30GB/s. Also, if multiple GDDR DRAMs are used simultaneously for higher bandwidth, then high power consumption and routing congestion on PCBs become a big concern. In order to overcome these limitations, the high-bandwidth memory (HBM) DRAM was recently introduced[1]. HBM-DRAM uses TSV and interposer technologies enabling multiple chip stacks and wide I/Os between the processor and memory: providing high capacity, low power and high bandwidth. This paper proposes the 2nd generation HBM to double the bandwidth from 128GB/s to more than 256GB/s and support pseudo-channel mode and 8H stacks [2]. In the pseudo-channel mode, a legacy channel is divided into two pseudo channels and the two pseudo channels share the command-address pins. Thus, one HBM has 16 pseudo channels instead of 8 legacy channels. To support various stack configurations including 8H stacks, a new architecture is adopted for flexible density ranging from 16Gb to 64Gb maintaining the same bandwidth. Finally, the bandwidth increase requires an active thermal solution to manage hotspots that develop from highly concentrated power consumption; we propose an adaptive refresh considering temperature distribution (ART) scheme as a solution.

Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs

For the demand of sever systems with high performance, high density and low power consumption, 3-D DDR4 SDRAM with TSVs was developed. In order to achieve higher data rate at lower voltage in comparison with precedent DDR3 SDRAM with TSVs, the placements of TSVs have been optimized without the penalty of chip size and the calibration method for reducing process mismatch between stacked DRAM chips is proposed. Additionally, new cell test method for stacked dies is adopted to keep costs down and the skewed self-refresh is proposed to reduce power noise. The IO speed of new DDR4 SDRAM with TSVs is increased to 2.4Gb/s at 1.2V.

17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs

As the demand for high-frequency DDR SDRAM increases, duty-cycle correction circuits (DCC) become a key element to widen the data-valid window (tDV). For duty detection in a DCC, analog schemes using charge pumps [1] and digital schemes using DLL locking [2] or time-to-digital converters (TDC) [3] are widely used. However, they require a certain amount of time proportional to duty errors or a high-resolution TDC to resolve quantization errors. For correction, an edge combiner or slew-rate-changing inverter is commonly used in DRAM applications. An edge combiner utilizes 180°-phase-shifted clocks, which are obtained by DLL locking or TDC code calculation [4-5], to generate both edges, but it has high-frequency limitations due to gate-delay-based short-pulse generation. The slew-rate-changing inverter has trade-offs between range and resolutions or between resolutions and DCC locking time. To achieve both wide range and fast locking, asynchronous binary search for detection and receiver tail-current tuning can be used for correction [6]. In a WCK-based system, duty and phase skew between iclk and qclk are related to the detection range. However, for normal DDR DRAM, this range should be doubled resulting in more area as well as locking time. To resolve problems with locking time, coverage, and resolution, a hybrid DCC is presented in this paper. For precise duty error detection, the phase and DCC locking processes should be separated, because delay updating disturbs duty-error detecting and averaging. In this paper, an all-digital DCC with TDC and an enhanced edge combiner performs fast DCC operation before DLL coarse locking, and a slew-rate-changing DCC optimized for fine resolution compensates quantization errors caused by all-digital operation.